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    Flexible flash commands
    4.
    发明授权
    Flexible flash commands 有权
    灵活的Flash命令

    公开(公告)号：US08645618B2

    公开(公告)日：2014-02-04

    申请号：US13332849

    申请日：2011-12-21

    申请人： Vinay Ashok Somanache ,  Jackson L. Ellis ,  Michael S. Hicken ,  Timothy W. Swatosh ,  Martin S. Dell ,  Pamela S. Hempstead

    发明人： Vinay Ashok Somanache ,  Jackson L. Ellis ,  Michael S. Hicken ,  Timothy W. Swatosh ,  Martin S. Dell ,  Pamela S. Hempstead

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1668

    摘要： A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context.

    摘要翻译： 一种控制闪存介质系统的方法。 该方法包括提供具有处理器控制模式并创建和呈现软上下文的闪存通道控制器。 软上下文通常将闪光灯通道控制器置于处理器控制模式。 在处理器控制模式下，闪存通道控制器存储整个软上下文，完成执行任何未完成的上下文，暂停正常的硬件自动化，然后执行软上下文。

    FLEXIBLE FLASH COMMANDS
    6.
    发明申请
    FLEXIBLE FLASH COMMANDS 有权
    灵活闪存命令

    公开(公告)号：US20130019050A1

    公开(公告)日：2013-01-17

    申请号：US13332849

    申请日：2011-12-21

    申请人： Vinay Ashok Somanache ,  Jackson L. Ellis ,  Michael S. Hicken ,  Timothy W. Swatosh ,  Martin S. Dell ,  Pamela S. Hempstead

    发明人： Vinay Ashok Somanache ,  Jackson L. Ellis ,  Michael S. Hicken ,  Timothy W. Swatosh ,  Martin S. Dell ,  Pamela S. Hempstead

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1668

    摘要： A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context.

    摘要翻译： 一种控制闪存介质系统的方法。 该方法包括提供具有处理器控制模式并创建和呈现软上下文的闪存通道控制器。 软上下文通常将闪光灯通道控制器置于处理器控制模式。 在处理器控制模式下，闪存通道控制器存储整个软上下文，完成执行任何未完成的上下文，暂停正常的硬件自动化，然后执行软上下文。

    Three-stage switch fabric with buffered crossbar devices
    7.
    发明授权
    Three-stage switch fabric with buffered crossbar devices 失效

    公开(公告)号：US07023841B2

    公开(公告)日：2006-04-04

    申请号：US10017174

    申请日：2001-12-14

    申请人： Martin S. Dell ,  Zbigniew M. Dziong ,  Wei Li ,  Matthew Tota ,  Yung-Terng Wang

    发明人： Martin S. Dell ,  Zbigniew M. Dziong ,  Wei Li ,  Matthew Tota ,  Yung-Terng Wang

    IPC分类号： H04L12/50

    CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L49/1576 ,  H04L49/3081 ,  H04L2012/5635 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04Q11/0478

    摘要： A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations. Each input device of the input stage transmits bids to the crossbar devices of the switching stage to request connections through the switching stage for routing the data to the output devices of the output stage. In one aspect, each crossbar device has (1) a bid arbitrator that determines whether to accept or reject each received bid, wherein, in response to a collision between multiple bids, the bid arbitrator accepts two or more of the colliding bids in a single time slot; and (2) memory for storing one or more accepted cells for the same output device, wherein the crossbar device can transmit grant signals for two or more accepted bids for the same output device in a single time slot. In another aspect, the bid arbitrator is configured to re-consider whether to accept a stored bid that was not accepted in a previous time slot.

    System with a plurality of media access control circuits with a shared memory for storing data and synchronizing data from a clock domain to a host clock domain
    8.
    发明授权
    System with a plurality of media access control circuits with a shared memory for storing data and synchronizing data from a clock domain to a host clock domain 有权
    具有多个具有共享存储器的媒体访问控制电路的系统，用于存储数据并将数据从时钟域同步到主机时钟域

    公开(公告)号：US06539488B1

    公开(公告)日：2003-03-25

    申请号：US09451295

    申请日：1999-11-30

    申请人： Matthew Tota ,  Martin S. Dell

    发明人： Matthew Tota ,  Martin S. Dell

    IPC分类号： G06F112

    CPC分类号： G06F5/06

    摘要： Integrated circuits are disclosed which implement multiple channel media access control devices for controlling network communications. The integrated circuits include multiple channel slices which output data for transmission through the network. Each of the channel data are input to a single data memory, which reduces the size of the integrated circuit. Since only one data memory is used to buffer data from multiple channels, the data are first retimed from individual media access control circuit clock domains to a common host clock domain and then scheduled for output to the host. By retiming the data, integrated circuit signal throughput is enhanced. Deeply embedded transmit and receive FIFOs are provided to receive the channel data and implement shared memory access.

    摘要翻译： 公开了实现用于控制网络通信的多信道媒体接入控制设备的集成电路。 集成电路包括输出数据以通过网络传输的多个通道片。 每个通道数据被输入到单个数据存储器，这减小了集成电路的尺寸。 由于仅使用一个数据存储器来缓冲来自多个通道的数据，因此首先将数据从各个媒体访问控制电路时钟域重新定时到公共主机时钟域，然后调度输出到主机。 通过重新定时数据，集成电路信号吞吐量得到提高。 提供深度嵌入式发送和接收FIFO来接收通道数据并实现共享存储器访问。

    Three-stage switch fabric with input device features
    9.
    发明授权
    Three-stage switch fabric with input device features 有权
    三级交换结构，具有输入设备特点

    公开(公告)号：US07161906B2

    公开(公告)日：2007-01-09

    申请号：US10017173

    申请日：2001-12-14

    申请人： Martin S. Dell ,  Zbigniew M. Dziong ,  Wei Li ,  Yu-Kuen Ouyang ,  Matthew Tota ,  Yung-Terng Wang

    发明人： Martin S. Dell ,  Zbigniew M. Dziong ,  Wei Li ,  Yu-Kuen Ouyang ,  Matthew Tota ,  Yung-Terng Wang

    IPC分类号： H04J1/16 ,  H04L12/66 ,  H04L12/28 ,  H04Q11/00

    CPC分类号： H04L49/1576 ,  H04L49/3081 ,  H04L2012/5634 ,  H04L2012/5635 ,  H04L2012/5679 ,  H04Q11/0005 ,  H04Q11/0478 ,  H04Q2011/0024 ,  H04Q2011/0052

    摘要： A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations. In one aspect, at least one input port can be programmably configured to store data in two or more input routing queues that are associated with a single output port, and at least one output port can be programmably configured to receive data from two or more output routing queues that are associated with a single input port. In another aspect, the output stage transmits status information about the output stage to the input stage, which uses the status information to generate bids to request connections through the switching stage. In yet another aspect, the switching stage transmits a grant/rejection signal to the input stage identifying (1) whether each bid is accepted or rejected and, if rejected, (2) a reason for rejecting the bid, and the input stage determines how to react to a rejected bid based on the reason the bid was rejected.

    摘要翻译： 用于路由数据的交换结构具有在输入级和输出级之间配置的切换级。 输入级将接收到的数据转发到切换级，该级将数据路由到输出级，将数据发送到目的地。 在一个方面，至少一个输入端口可以可编程地配置为将数据存储在与单个输出端口相关联的两个或多个输入路由队列中，并且至少一个输出端口可以被可编程地配置成从两个或更多个输出端接收数据 与单个输入端口关联的路由队列。 在另一方面，输出级将关于输出级的状态信息发送到输入级，其使用状态信息来生成出价以请求通过切换级的连接。 在另一方面，切换阶段向准入/拒绝信号发送授权/拒绝信号，识别（1）是否接受或拒绝每个投标，如果被拒绝，则拒绝该投标的原因，并且输入阶段确定如何 根据拒绝的原因对拒绝的投标做出反应。

    Scheduler for a packet routing and switching system
    10.
    发明授权
    Scheduler for a packet routing and switching system 有权
    分组路由和交换系统的调度程序

    公开(公告)号：US07158528B2

    公开(公告)日：2007-01-02

    申请号：US10017503

    申请日：2001-12-14

    申请人： Martin S. Dell ,  John Leshchuk ,  Wei Li ,  Walter A. Roper ,  Matthew Tota

    发明人： Martin S. Dell ,  John Leshchuk ,  Wei Li ,  Walter A. Roper ,  Matthew Tota

    IPC分类号： H04L12/28

    CPC分类号： H04L47/56 ,  H04L47/50 ,  H04L47/527 ,  H04L49/254

    摘要： In one embodiment, queues associated with a first traffic class (FTC) are selected for service. Each FTC queue having at least one enqueued cell is identified as an occupied FTC queue, Where at least one FTC queue is provisioned for burst scheduling of multiple cells when serviced. An occupied FTC queue provisioned for burst scheduling is identified as a super-occupied FTC queue when the number of cells enqueued is greater than a specified number. Each occupied FTC queue is set as eligible for service based on a FTC scheduling algorithm. An eligible FTC queue is selected for service based on a corresponding sub-priority of each eligible FTC queue. Each FTC queue is assigned a sub-priority based on a service level of a connection associated with enqueued cells. When the super-occupied queue is serviced, the number of cells dequeued is based on a burst size.

    摘要翻译： 在一个实施例中，选择与第一业务类别（FTC）相关联的队列进行服务。 具有至少一个入队单元的每个FTC队列被识别为被占用的FTC队列。当被服务时，至少提供一个FTC队列用于多个小区的突发调度。 当排队的单元数大于指定数量时，为突发调度提供的被占用的FTC队列被识别为超占用的FTC队列。 基于FTC调度算法将每个占用的FTC队列设置为符合服务条件。 基于每个合格的FTC队列的相应子优先级，选择合格的FTC队列进行服务。 根据与入队单元相关联的连接的服务级别，为每个FTC队列分配一个子优先级。 当超占用队列被服务时，出队的单元数量是基于突发大小的。