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1.发明授权System and method for dynamically configurable multi-window divergent protocol bridge 有权用于动态配置多窗口发散协议桥的系统和方法公开(公告)号：US08831021B2
公开(公告)日：2014-09-09
申请号：US13244538
申请日：2011-09-25
IPC分类号： H04L12/56
CPC分类号： G06F13/4045
摘要： A bridge interfaces a first network protocol and a second network interface protocol. Each of a plurality of mapping windows is defined by corresponding mapping parameters defining a space in the first protocol and defining the mapping window translation rules to the second network protocol. Transaction requests in the first network protocol are selectively associated with the mapping windows.
摘要翻译： 桥接接口第一网络协议和第二网络接口协议。 多个映射窗口中的每一个由定义第一协议中的空间的对应映射参数定义，并将映射窗口转换规则定义到第二网络协议。 第一网络协议中的事务请求与映射窗口有选择地关联。
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2.发明申请System and Method for Dynamically Configurable Multi-Window Divergent Protocol Bridge 有权用于动态配置的多窗口发散协议桥的系统和方法公开(公告)号：US20130077635A1
公开(公告)日：2013-03-28
申请号：US13244538
申请日：2011-09-25
IPC分类号： H04L12/56
CPC分类号： G06F13/4045
摘要： A bridge interfaces a first network protocol and a second network interface protocol. Each of a plurality of mapping windows is defined by corresponding mapping parameters defining a space in the first protocol and defining the mapping window translation rules to the second network protocol. Transaction requests in the first network protocol are selectively associated with the mapping windows.
摘要翻译： 桥接接口第一网络协议和第二网络接口协议。 多个映射窗口中的每一个由定义第一协议中的空间的对应映射参数定义，并将映射窗口转换规则定义到第二网络协议。 第一网络协议中的事务请求与映射窗口有选择地关联。
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3.发明授权公开(公告)号：US08611178B2
公开(公告)日：2013-12-17
申请号：US13294944
申请日：2011-11-11
IPC分类号： G11C8/16
CPC分类号： G06F13/1689
摘要： A device and method to perform memory operations at a clock domain crossing is disclosed. In a particular embodiment, a method includes providing a first clock signal to a write clock input of a memory to write data to the memory. The data is read from the memory according to a second clock signal that is different from the first clock signal. A third clock signal is provided to a read clock input of the memory. The third clock signal has a frequency that is substantially an integer multiple of a frequency of the second clock signal. The integer multiple is greater than one.
摘要翻译： 公开了一种在时钟域交叉处执行存储器操作的装置和方法。 在特定实施例中，一种方法包括向存储器的写时钟输入提供第一时钟信号以将数据写入存储器。 根据与第一时钟信号不同的第二时钟信号从存储器读取数据。 第三时钟信号被提供给存储器的读取时钟输入。 第三时钟信号具有基本上是第二时钟信号的频率的整数倍的频率。 整数倍大于1。
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4.发明申请公开(公告)号：US20130121100A1
公开(公告)日：2013-05-16
申请号：US13294944
申请日：2011-11-11
IPC分类号： G11C8/18
CPC分类号： G06F13/1689
摘要： A device and method to perform memory operations at a clock domain crossing is disclosed. In a particular embodiment, a method includes providing a first clock signal to a write clock input of a memory to write data to the memory. The data is read from the memory according to a second clock signal that is different from the first clock signal. A third clock signal is provided to a read clock input of the memory. The third clock signal has a frequency that is substantially an integer multiple of a frequency of the second clock signal. The integer multiple is greater than one.
摘要翻译： 公开了一种在时钟域交叉处执行存储器操作的装置和方法。 在特定实施例中，一种方法包括向存储器的写时钟输入提供第一时钟信号以将数据写入存储器。 根据与第一时钟信号不同的第二时钟信号从存储器读取数据。 第三时钟信号被提供给存储器的读取时钟输入。 第三时钟信号具有基本上是第二时钟信号的频率的整数倍的频率。 整数倍大于1。
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公开(公告)号：US07116143B2
公开(公告)日：2006-10-03
申请号：US11027343
申请日：2004-12-30
IPC分类号： H03L7/06
CPC分类号： H03K5/1565 , G06F1/04 , G11C7/22 , G11C7/222 , H03K5/135 , H03L7/0814
摘要： A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.
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公开(公告)号：US07250798B2
公开(公告)日：2007-07-31
申请号：US11417390
申请日：2006-05-03
IPC分类号： H03L7/06
CPC分类号： H03K5/1565 , G06F1/04 , G11C7/22 , G11C7/222 , H03K5/135 , H03L7/0814
摘要： A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.
摘要翻译： 一种时钟发生器，用于产生与输入时钟信号同步并具有校正占空比的输出时钟信号。 时钟发生器包括输入缓冲器以缓冲输入时钟信号并产生缓冲的时钟信号和输出缓冲器，以响应于施加到第一和第二输入端的第一和第二时钟信号而产生输出时钟信号。 耦合到输入缓冲器的输出并耦合到输出缓冲器的第一和第二输入的可调延迟环具有单个反馈延迟环，并被配置为产生第一时钟信号和第二时钟信号。 第二个时钟信号与第一个时钟信号相差180度。
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公开(公告)号：US07208989B2
公开(公告)日：2007-04-24
申请号：US11437040
申请日：2006-05-19
IPC分类号： H03L7/06
CPC分类号： H03K5/1565 , G06F1/04 , G11C7/22 , G11C7/222 , H03K5/135 , H03L7/0814
摘要： A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.
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