公开(公告)号：US20240013871A1

公开(公告)日：2024-01-11

申请号：US18043164

申请日：2021-08-27

Applicant: Vivek Asthana ,  Ankur Agrawal

Inventor： Vivek Asthana ,  Ankur Agrawal

IPC: G16H10/20 ,  G16H20/00 ,  G16H10/60

CPC classification number: G16H10/20 ,  G16H20/00 ,  G16H10/60

Abstract: A SaaS platform to manage a clinical trial is disclosed. The platform enables on-boarding of patients for the clinical trial for one or more clinical research organizations. Such details are necessary for categorisation of the one or more patients. A medical compliance module is set up to capture real time bio-physical parameters indicative of health condition of the patients. The medical compliance module also monitors adherence of each of the patients to the one or more treatment plans designed for the clinical trials. Additionally, a database management module receives, and stores data associated with the clinical trial from the one or more clinical research organisations. Storing of such classified data is being done with specific privacy level for security. An access control module further enables collaborative clinical trial among the one or more clinical research organisations by sharing the data associated with the clinical trial in real-time.

公开(公告)号：US08767428B2

公开(公告)日：2014-07-01

申请号：US13172665

申请日：2011-06-29

Applicant: Vivek Asthana

Inventor： Vivek Asthana

IPC: G11C15/00

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract translation: 存储器体包括存储器单元和用于确定存储体的工作电压的附加单元。 附加单元具有小于存储体中其它存储单元的对应操作裕度的操作裕度。

公开(公告)号：US20140003135A1

公开(公告)日：2014-01-02

申请号：US13539577

申请日：2012-07-02

Applicant: Vivek Asthana ,  Malathi Kar ,  Philippe Galy ,  Jean Jimenez

Inventor： Vivek Asthana ,  Malathi Kar ,  Philippe Galy ,  Jean Jimenez

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/4125 ,  G11C11/419

Abstract: An SRAM bitcell includes first and second CMOS inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes. A first direct connection is provided between the true bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the second CMOS inverter. A second direct connection is provided between the complement bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the first CMOS inverter. A first pass transistor is coupled between the true bitline node and the true node, and a second pass transistor is coupled between the complement bitline node and the complement node. Direct connections are also provided between a wordline and the back gates of each of the first and second pass transistors.

Abstract translation: SRAM位单元包括作为锁存器连接的第一和第二CMOS反相器，其定义真实节点和补码节点。 位单元还包括真和补码位线节点。 在第二CMOS反相器中，在真位线节点和至少p沟道晶体管的背栅极之间提供第一直接连接，以及可能还提供n沟道晶体管。 在第一CMOS反相器中的补码位线节点和至少p沟道晶体管的背栅极之间提供第二直接连接，以及可能还提供n沟道晶体管。 第一传输晶体管耦合在真位元节点和真节点之间，第二传输晶体管耦合在补码位线节点和补码节点之间。 在字线和第一和第二传输晶体管的每个的后栅极之间也提供直接连接。

公开(公告)号：US09159402B2

公开(公告)日：2015-10-13

申请号：US13539577

申请日：2012-07-02

Applicant: Vivek Asthana ,  Malathi Kar ,  Philippe Galy ,  Jean Jimenez

Inventor： Vivek Asthana ,  Malathi Kar ,  Philippe Galy ,  Jean Jimenez

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/4125 ,  G11C11/419

Abstract: An SRAM bitcell includes first and second CMOS inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes. A first direct connection is provided between the true bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the second CMOS inverter. A second direct connection is provided between the complement bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the first CMOS inverter. A first pass transistor is coupled between the true bitline node and the true node, and a second pass transistor is coupled between the complement bitline node and the complement node. Direct connections are also provided between a wordline and the back gates of each of the first and second pass transistors.

Abstract translation: SRAM位单元包括作为锁存器连接的第一和第二CMOS反相器，其定义真实节点和补码节点。 位单元还包括真和补码位线节点。 在第二CMOS反相器中，在真位线节点和至少p沟道晶体管的背栅极之间提供第一直接连接，以及可能还提供n沟道晶体管。 在第一CMOS反相器中的补码位线节点和至少p沟道晶体管的背栅极之间提供第二直接连接，以及可能还提供n沟道晶体管。 第一传输晶体管耦合在真位元节点和真节点之间，第二传输晶体管耦合在补码位线节点和补码节点之间。 在字线和第一和第二传输晶体管的每个的后栅极之间也提供直接连接。

公开(公告)号：US20130003442A1

公开(公告)日：2013-01-03

申请号：US13172665

申请日：2011-06-29

Applicant: Vivek Asthana

Inventor： Vivek Asthana

IPC: G11C11/00 ,  G11C8/00

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract translation: 存储器体包括存储器单元和用于确定存储体的工作电压的附加单元。 附加单元具有小于存储体中其它存储单元的对应操作裕度的操作裕度。

公开(公告)号：US20070201270A1

公开(公告)日：2007-08-30

申请号：US11648155

申请日：2006-12-29

Applicant: Kallol Chatterjee ,  Vivek Asthana ,  Jitendra Dasani

Inventor： Kallol Chatterjee ,  Vivek Asthana ,  Jitendra Dasani

IPC: G11C16/04

CPC classification number: G11C17/10

Abstract: A memory chip configuration aims that reduces the bitline leakage in standby as well as dynamic operation mode. The chip design comprises of—a n×m FET matrix, vertically running bitlines—each shared by a column in the array, horizontally running wordlines—each shared by a row in the array, horizontally running sourcelines—each shared by a row in the array. The sourceline signal for a row is generated by complementing the wordline signal for the same row. The memory cell read operations with the proposed configuration, substantially control the bitline leakage current thereby enhancing the memory speed by reducing the noise during read operations. Also the configuration is unconstrained by design parameters that include size and geometries of memory chips, cell densities, complexity of memory structures, fabrication technologies, etc.

Abstract translation: 存储器芯片配置旨在减少待机和动态操作模式下的位线泄漏。 芯片设计包括一个nxm FET矩阵，垂直运行的位线，每个位线由数组中的一个列共享，每个数组水平运行的字线，每个字段由数组中的一个行共享，水平运行源线，每个数组都由数组中的一行共享。 通过对同一行的字线信号进行补码来生成行的源极线信号。 利用所提出的配置，存储单元读取操作，基本上控制位线泄漏电流，从而通过降低读取操作期间的噪声来增强存储器速度。 此外，该配置不受包括存储器芯片的尺寸和几何形状，单元密度，存储器结构的复杂性，制造技术等的设计参数的约束。