公开(公告)号：US20100327932A1

公开(公告)日：2010-12-30

申请号：US12492541

申请日：2009-06-26

申请人： Vladimir Aparin ,  Gary J. Ballantyne

发明人： Vladimir Aparin ,  Gary J. Ballantyne

IPC分类号： H03H11/16

CPC分类号： H04B1/0475

摘要： Techniques for improving stability of a feedback system are described. In an exemplary design, the feedback system includes a forward path and a feedback path. The forward path receives an input signal and a rotated feedback signal and provides an output signal having a phase shift. The feedback path receives the output signal, generates a feedback signal, and rotates the feedback signal to obtain the rotated feedback signal having at least part of the phase shift removed. In another exemplary design, the feedback system includes a forward path and a feedback loop. The forward path receives a combined signal and provides an output signal having a phase shift. The feedback loop generates an error signal based on an input signal and the output signal, generates the combined signal based on the error signal and the input signal, and performs phase rotation to remove at least part of the phase shift.

摘要翻译： 描述了提高反馈系统稳定性的技术。 在示例性设计中，反馈系统包括前向路径和反馈路径。 正向路径接收输入信号和旋转的反馈信号，并提供具有相移的输出信号。 反馈路径接收输出信号，产生反馈信号，并且使反馈信号旋转以获得具有至少部分相移的旋转的反馈信号。 在另一示例性设计中，反馈系统包括前向路径和反馈回路。 正向路径接收组合信号并提供具有相移的输出信号。 反馈回路基于输入信号和输出信号产生误差信号，基于误差信号和输入信号产生组合信号，并执行相位旋转以去除至少部分相移。

公开(公告)号：US09129220B2

公开(公告)日：2015-09-08

申请号：US12831871

申请日：2010-07-07

申请人： Vladimir Aparin ,  Subramaniam Venkatraman

发明人： Vladimir Aparin ,  Subramaniam Venkatraman

IPC分类号： G06F15/18 ,  G06N3/04 ,  G06N3/063

CPC分类号： G06N3/049 ,  G06N3/0472 ,  G06N3/063

摘要： Certain embodiments of the present disclosure support implementation of a digital neural processor with discrete-level synapses and probabilistic synapse weight training.

摘要翻译： 本公开的某些实施例支持具有离散级突触和概率突触重量训练的数字神经处理器的实现。

公开(公告)号：US08618876B2

公开(公告)日：2013-12-31

申请号：US12130729

申请日：2008-05-30

申请人： Junxiong Deng ,  Gurkanwal Singh Sahota ,  Prashanth Akula ,  Thomas Marra ,  Vladimir Aparin

发明人： Junxiong Deng ,  Gurkanwal Singh Sahota ,  Prashanth Akula ,  Thomas Marra ,  Vladimir Aparin

IPC分类号： H03F1/14

CPC分类号： H04B1/04 ,  H03F1/0261 ,  H03F3/24 ,  H03F2200/321 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/537

摘要： An exemplary embodiment discloses a digital control block for dynamically regulating power consumption of the transmitter; and a first driver amplifier circuit comprising a plurality of bias-modes each corresponding to a power consumption level in the transmitter, the digital control block to instruct the first driver amplifier circuit to operate in a selected bias-mode to regulate power consumption of the transmitter.

摘要翻译： 示例性实施例公开了一种用于动态调节发射机的功率消耗的数字控制块; 以及第一驱动器放大器电路，其包括多个偏置模式，每个偏置模式对应于所述发射器中的功率消耗水平，所述数字控制块指示所述第一驱动器放大器电路以选定的偏置模式操作以调节所述发射器的功率消耗 。

公开(公告)号：US20120303566A1

公开(公告)日：2012-11-29

申请号：US13115154

申请日：2011-05-25

申请人： Vladimir Aparin

发明人： Vladimir Aparin

IPC分类号： G06N3/08 ,  G06N3/063

CPC分类号： G06N3/063

摘要： Certain aspects of the present disclosure present a technique for unsupervised training of input synapses of primary visual cortex (V1) simple cells and other neural circuits. The proposed unsupervised training method utilizes simple neuron models for both Retinal Ganglion Cell (RGC) and V1 layers. The model simply adds the weighted inputs of each cell, wherein the inputs can have positive or negative values. The resulting weighted sums of inputs represent activations that can also be positive or negative. In an aspect of the present disclosure, the weights of each V1 cell can be adjusted depending on a sign of corresponding RGC output and a sign of activation of that V1 cell in the direction of increasing the absolute value of the activation. The RGC-to-V1 weights can be positive and negative for modeling ON and OFF RGCs, respectively.

摘要翻译： 本公开的某些方面提供了用于无监督训练初级视皮层（V1）简单细胞和其他神经电路的输入突触的技术。 提出的无监督训练方法使用简单的神经元模型用于视网膜神经节细胞（RGC）和V1层。 该模型简单地添加每个单元的加权输入，其中输入可以具有正值或负值。 所得的加权输入总和代表也可以是正或负的激活。 在本公开的一方面，可以根据对应的RGC输出的符号和在增加激活的绝对值的方向激活该V1小区的符号来调整每个V1小区的权重。 RGC-to-V1权重可以分别为ON和OFF RGC的正负值。

公开(公告)号：US20120236958A1

公开(公告)日：2012-09-20

申请号：US12130729

申请日：2008-05-30

申请人： Junxiong Deng ,  Gurkanwal Singh Sahota ,  Prashanth Akula ,  Thomas Marra ,  Vladimir Aparin

发明人： Junxiong Deng ,  Gurkanwal Singh Sahota ,  Prashanth Akula ,  Thomas Marra ,  Vladimir Aparin

IPC分类号： H04L27/00

CPC分类号： H04B1/04 ,  H03F1/0261 ,  H03F3/24 ,  H03F2200/321 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/537

摘要： An exemplary embodiment discloses a digital control block for dynamically regulating power consumption of the transmitter; and a first driver amplifier circuit comprising a plurality of bias-modes each corresponding to a power consumption level in the transmitter, the digital control block to instruct the first driver amplifier circuit to operate in a selected bias-mode to regulate power consumption of the transmitter.

摘要翻译： 示例性实施例公开了一种用于动态调节发射机的功率消耗的数字控制块; 以及第一驱动器放大器电路，其包括多个偏置模式，每个偏置模式对应于所述发射器中的功率消耗水平，所述数字控制块指示所述第一驱动器放大器电路以选定的偏置模式操作以调节所述发射器的功率消耗 。

公开(公告)号：US20120211812A1

公开(公告)日：2012-08-23

申请号：US13103918

申请日：2011-05-09

申请人： Yang Du ,  Vladimir Aparin ,  Robert P. Gilmore

发明人： Yang Du ,  Vladimir Aparin ,  Robert P. Gilmore

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/42384 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/78645

摘要： High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.

摘要翻译： 公开了高速大功率半导体器件。 在示例性设计中，高速大功率半导体器件包括源极，提供输出信号的漏极和用于接收输入信号的有源栅极。 所述半导体器件还包括位于有源栅极和漏极之间的至少一个场栅极，至少一个横向于至少一个场栅极形成的浅沟槽隔离（STI）条和至少一个平行于该栅极的漏极有源条， 并与所述至少一个STI条交替。 半导体器件可以通过有源FET和MOS变容二极管的组合来建模。 有源栅极控制有源FET，并且至少一个场门控制MOS变容二极管。 半导体器件具有低导通电阻并且可以处理高电压。

公开(公告)号：US20120011090A1

公开(公告)日：2012-01-12

申请号：US12831594

申请日：2010-07-07

申请人： Yi Tang ,  Jeffrey A. Levin ,  Vladimir Aparin ,  Venkat Rangan

发明人： Yi Tang ,  Jeffrey A. Levin ,  Vladimir Aparin ,  Venkat Rangan

IPC分类号： G06N3/063

CPC分类号： G06N3/0635 ,  G06N3/049

摘要： The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling.

摘要翻译： 本公开提出了三忆阻突触的实施，其中突触强度的调整基于具有多巴胺信号传导的尖峰时间依赖性可塑性（STDP）。

公开(公告)号：US20120011088A1

公开(公告)日：2012-01-12

申请号：US12831540

申请日：2010-07-07

申请人： Vladimir Aparin ,  Yi Tang

发明人： Vladimir Aparin ,  Yi Tang

IPC分类号： G06N3/063 ,  G06N3/08

CPC分类号： G06N3/0635 ,  G06N3/02 ,  G06N3/06 ,  G06N3/08 ,  G06N99/005

摘要： Certain embodiments of the present disclosure support techniques for training of synapses in biologically inspired networks. Only one device based on a memristor can be used as a synaptic connection between a pair of neurons. The training of synaptic weights can be achieved with a low current consumption. A proposed synapse training circuit may be shared by a plurality of incoming/outgoing connections, while only one digitally implemented pulse-width modulation (PWM) generator can be utilized per neuron circuit for generating synapse-training pulses. Only up to three phases of a slow clock can be used for both the neuron-to-neuron communications and synapse training. Some special control signals can be also generated for setting up synapse training events. By means of these signals, the synapse training circuit can be in a high-impedance state outside the training events, thus the synaptic resistance (i.e., the synaptic weight) is not affected outside the training process.

摘要翻译： 本公开的某些实施例支持在生物启发网络中训练突触的技术。 只有一个基于忆阻器的设备可以用作一对神经元之间的突触连接。 突触体重的训练可以用低电流消耗来实现。 所提出的突触训练电路可以由多个输入/输出连接共享，而每个神经元电路只能使用一个数字实现的脉宽调制（PWM）发生器来产生突触训练脉冲。 只有三个阶段的慢时钟可以用于神经元到神经元通信和突触训练。 还可以生成一些特殊的控制信号来设置突触训练事件。 通过这些信号，突触训练电路可以在训练事件之外处于高阻抗状态，因此在训练过程之外不会影响突触电阻（即突触重量）。

公开(公告)号：US20100323641A1

公开(公告)日：2010-12-23

申请号：US12489380

申请日：2009-06-22

申请人： Vladimir Aparin ,  Gary John Ballantyne

发明人： Vladimir Aparin ,  Gary John Ballantyne

IPC分类号： H04B1/04

CPC分类号： H03F1/34 ,  H03F1/3258

摘要： Techniques for mitigating nonlinearity of circuits with both pre-distortion and feedback are described. An apparatus may include at least one circuit (e.g., an upconverter, a power amplifier, etc.), a pre-distortion circuit, and a feedback circuit. The circuit(s) may generate an output signal having distortion components due to their nonlinearity. The pre-distortion circuit may receive an input signal and generate a pre-distorted signal based on at least one coefficient determined by the nonlinearity of the circuit(s). The pre-distortion circuit may adaptively determine the coefficient(s) based on the input signal and an error signal. The feedback circuit may generate the error signal based on the input signal and the output signal and may filter the error signal to obtain a filtered error signal. The circuit(s) may process the pre-distorted signal and the filtered error signal to generate the output signal, which may have attenuated distortion components due to pre-distortion and feedback.

摘要翻译： 描述了减轻预失真和反馈的电路非线性的技术。 装置可以包括至少一个电路（例如，上变频器，功率放大器等），预失真电路和反馈电路。 电路可以由于它们的非线性而产生具有失真分量的输出信号。 预失真电路可以接收输入信号，并且基于由电路的非线性确定的至少一个系数产生预失真信号。 预失真电路可以基于输入信号和误差信号自适应地确定系数。 反馈电路可以基于输入信号和输出信号产生误差信号，并且可以对误差信号进行滤波以获得滤波后的误差信号。 电路可以处理预失真信号和滤波后的误差信号以产生输出信号，其可能由于预失真和反馈而具有衰减的失真分量。

公开(公告)号：US20080233894A1

公开(公告)日：2008-09-25

申请号：US11690173

申请日：2007-03-23

申请人： Vladimir Aparin

发明人： Vladimir Aparin

IPC分类号： H04B1/44

CPC分类号： H04B1/525 ,  H04B1/30

摘要： This disclosure describes techniques for reducing adverse effects of TX signal leakage in a full-duplex, wireless communication system. In particular, the disclosure describes techniques for reducing adverse effects of second order distortion of TX signal leakage. To reduce or eliminate second order distortion of transmit signal leakage, a wireless device squares a combined signal that carries both a desired RX signal and a TX leakage signal. For example, the device may include a device that exhibits a strong, second order nonlinearity to, in effect, square the combined signal. The device subtracts the squared signal from the output of the mixer in the receive path, canceling out at least some of the second-order distortion caused by the mixer. In this manner, the device can reduce the adverse effects of second order distortion of TX signal leakage, and thereby enhance or maintain receiver sensitivity.

摘要翻译： 本公开描述了用于减少全双工无线通信系统中TX信号泄漏的不利影响的技术。 具体地，本公开描述了用于减少TX信号泄漏的二阶失真的不利影响的技术。 为了减少或消除发射信号泄漏的二阶失真，无线设备对携带期望的RX信号和TX泄漏信号的组合信号进行平方。 例如，该装置可以包括展现强的二阶非线性的装置，其实际上对于组合信号的平方。 该装置从接收路径中的混频器的输出中减去平方信号，消除由混频器引起的至少一些二阶失真。 以这种方式，该装置可以减少TX信号泄漏的二阶失真的不利影响，从而提高或维持接收机灵敏度。