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公开(公告)号：US20130142245A1
公开(公告)日：2013-06-06
申请号：US13312443
申请日：2011-12-06
申请人： Vladimir Sindalovsky , Mohammed S. Mobin , Lane A. Smith , Amaresh V. Malipatil , Pervez M. Aziz
发明人： Vladimir Sindalovsky , Mohammed S. Mobin , Lane A. Smith , Amaresh V. Malipatil , Pervez M. Aziz
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L2025/03636 , H04L2025/03694
摘要： In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.
摘要翻译： 在所描述的实施例中，串行器解串器（SerDes）接收器包括模式检测器，其允许检测到不充分随机的模式周期和低活动期。 在这些时期内冻结均衡适应可能会通过将不合格的模式嵌入到适应数据中来实现。 一些实施例还允许检测长的冻结间隔，并且因此延迟冻结断言以便接收器的时钟和数据恢复（CDR）电路重新获得对串行数据的锁定。 在接收数据中嵌入冻结信息可以精确地同步接收数据并进行冻结。
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公开(公告)号：US08548038B2
公开(公告)日：2013-10-01
申请号：US13312443
申请日：2011-12-06
申请人： Vladimir Sindalovsky , Mohammad S. Mobin , Lane A. Smith , Amaresh V. Malipatil , Pervez M. Aziz
发明人： Vladimir Sindalovsky , Mohammad S. Mobin , Lane A. Smith , Amaresh V. Malipatil , Pervez M. Aziz
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/03636 , H04L2025/03694
摘要： In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.
摘要翻译： 在所描述的实施例中，串行器解串器（SerDes）接收器包括模式检测器，其允许检测到不充分随机的模式周期和低活动期。 在这些时期内冻结均衡适应可能会通过将不合格的模式嵌入到适应数据中来实现。 一些实施例还允许检测长的冻结间隔，并且因此延迟冻结断言以便接收器的时钟和数据恢复（CDR）电路重新获得对串行数据的锁定。 在接收数据中嵌入冻结信息可以精确地同步接收数据并进行冻结。
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3.发明授权Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern 有权用于在存在不利模式的情况下使用DFE检测数据产生用于判决反馈均衡器的一个或多个时钟信号的方法和装置公开(公告)号：US07599461B2
公开(公告)日：2009-10-06
申请号：US11541498
申请日：2006-09-29
IPC分类号： H03D3/24
CPC分类号： H04L25/03057 , H04L7/0062
摘要： Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist pattern. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. One or more of said phase updates are modified by the present invention if said DFE detected data satisfies one or more predefined conditions. A number of mechanisms are disclosed for qualifying or modifying the DFE phase detector updates based on the detected data pattern.
摘要翻译： 提供的方法和装置用于在诸如奈奎斯特图案之类的不利图案的存在下，使用DFE检测数据产生用于判决反馈均衡器的一个或多个时钟信号。 使用数据时钟和转换时钟对接收到的信号进行采样，以生成数据采样信号和转换采样信号。 为每个数据采样和转换采样信号获得DFE校正，以产生DFE检测数据和DFE转换数据。 DFE检测数据和DFE转换数据然后被施加到产生信号以调整数据时钟和转换时钟中的一个或多个的相位的相位检测器。 如果所述DFE检测到的数据满足一个或多个预定条件，则本发明修改所述相位更新中的一个或多个。 公开了用于基于检测到的数据模式来限定或修改DFE相位检测器更新的多种机制。
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4.发明申请Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern 有权用于在存在不利模式的情况下使用DFE检测数据产生用于判决反馈均衡器的一个或多个时钟信号的方法和装置公开(公告)号：US20080080610A1
公开(公告)日：2008-04-03
申请号：US11541498
申请日：2006-09-29
CPC分类号： H04L25/03057 , H04L7/0062
摘要： Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist pattern. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. One or more of said phase updates are modified by the present invention if said DFE detected data satisfies one or more predefined conditions. A number of mechanisms are disclosed for qualifying or modifying the DFE phase detector updates based on the detected data pattern.
摘要翻译： 提供的方法和装置用于在诸如奈奎斯特图案之类的不利图案的存在下，使用DFE检测数据产生用于判决反馈均衡器的一个或多个时钟信号。 使用数据时钟和转换时钟对接收到的信号进行采样，以生成数据采样信号和转换采样信号。 为每个数据采样和转换采样信号获得DFE校正，以产生DFE检测数据和DFE转换数据。 DFE检测数据和DFE转换数据然后被施加到产生信号以调整数据时钟和转换时钟中的一个或多个的相位的相位检测器。 如果所述DFE检测到的数据满足一个或多个预定条件，则本发明修改所述相位更新中的一个或多个。 公开了用于基于检测到的数据模式来限定或修改DFE相位检测器更新的多种机制。
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5.发明授权公开(公告)号：US08743945B2
公开(公告)日：2014-06-03
申请号：US13540923
申请日：2012-07-03
IPC分类号： H03H7/30
CPC分类号： H04L25/14 , H04L25/03057 , H04L25/03885 , H04L2025/0349 , H04L2025/03579
摘要： Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.
摘要翻译： 描述的实施例通过一组固定抽头和接收器的一组浮动抽头接收信号，每个抽头对应于检测到的符号。 每个浮动抽头存储在相应的移位寄存器中，以解决接收器的过程，工作电压和温度（PVT）变化，而不校准延迟元件。 多路复用逻辑通过将选定的浮动抽头耦合到固定抽头的输出端，选择（i）相应的浮动抽头进行均衡，以及（ii）每个可能的浮动抽头位置的不同相位。 多路复用逻辑修剪和/或合并每个可能的浮动抽头位置的相位，并且基于每相的幅度选择浮动抽头。 组合器通过相应的抽头调整固定抽头和所选浮动抽头的每个输出值，将调整后的值组合成输出信号，并从输入信号中减去输出信号。
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6.发明申请公开(公告)号：US20130230093A1
公开(公告)日：2013-09-05
申请号：US13540923
申请日：2012-07-03
IPC分类号： H04L27/01
CPC分类号： H04L25/14 , H04L25/03057 , H04L25/03885 , H04L2025/0349 , H04L2025/03579
摘要： Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.
摘要翻译： 描述的实施例通过一组固定抽头和接收器的一组浮动抽头接收信号，每个抽头对应于检测到的符号。 每个浮动抽头存储在相应的移位寄存器中，以解决接收器的过程，工作电压和温度（PVT）变化，而不校准延迟元件。 多路复用逻辑通过将选定的浮动抽头耦合到固定抽头的输出端，选择（i）相应的浮动抽头进行均衡，以及（ii）每个可能的浮动抽头位置的不同相位。 多路复用逻辑修剪和/或合并每个可能的浮动抽头位置的相位，并且基于每相的幅度选择浮动抽头。 组合器通过相应的抽头调整固定抽头和所选浮动抽头的每个输出值，将调整后的值组合成输出信号，并从输入信号中减去输出信号。
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7.发明申请METHOD AND APPARATUS FOR INTEGRAL STATE INITIALIZATION AND QUALITY OF LOCK MONITORING IN A CLOCK AND DATA RECOVERY SYSTEM 有权综合状态初始化和时钟和数据恢复系统中的监控质量的方法与装置公开(公告)号：US20100290513A1
公开(公告)日：2010-11-18
申请号：US12846390
申请日：2010-07-29
IPC分类号： H04B17/00
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译： 提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。 还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。 通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。
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8.发明授权Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量公开(公告)号：US07792234B2
公开(公告)日：2010-09-07
申请号：US11414521
申请日：2006-04-28
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译： 提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。 还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。 通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。
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9.发明授权Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量公开(公告)号：US08416907B2
公开(公告)日：2013-04-09
申请号：US12846390
申请日：2010-07-29
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译： 提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。 还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。 通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。
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公开(公告)号：US08432959B2
公开(公告)日：2013-04-30
申请号：US11930814
申请日：2007-10-31
CPC分类号： H04L25/0262 , H04L25/03006 , H04L25/03057 , H04L2025/03375 , H04L2025/03535 , H04L2025/03726
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step.
摘要翻译： 提供了用于均衡接收信号的方法和装置。 通过更新一个或多个均衡参数来使接收信号相等; 以及如果在均衡步骤期间检测到一个或多个预定义的限定条件，则丢弃所述更新的均衡参数。 如果在平衡步骤期间未检测到预定义的限定条件，则可以使用更新的均衡参数来选择性地均衡所接收的信号。 如果在均衡步骤期间未检测到一个或多个预定义限定条件，则可以可选地存储更新的均衡参数。
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