-
公开(公告)号：US10311819B2
公开(公告)日：2019-06-04
申请号：US15511016
申请日：2017-02-17
Inventor： Shijuan Yi
Abstract: The invention provides a CMOS GOA circuit, comprising a signal processing module having a first and a second TFTs, the first TFT having a gate connected to a first control signal, a source connected to an output node and a drain connected to a third node; the second TFT having a gate and a source connected to a second control signal, and a drain connected to the third node; the first and second control signals having opposite phases, the first and second control signals controlling the first and second TFTs to turn on alternatingly inputting a voltage signal of the output node or a second control signal to the third node. Compared to the known technique using NAND circuit, the invention reduces the number of TFTs required by latch module without affecting operation of the circuit, and facilitates the implementation of the ultra-narrow border or borderless display products.
-
公开(公告)号：US10032425B2
公开(公告)日：2018-07-24
申请号：US15119385
申请日：2016-05-25
Inventor： Shijuan Yi , Mang Zhao
Abstract: The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N−2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.
-
公开(公告)号：US20200219957A1
公开(公告)日：2020-07-09
申请号：US16819199
申请日：2020-03-16
Inventor： Shijuan Yi , Shuang Li
IPC: H01L27/32 , H01L51/50 , G09G3/3225 , H01L51/56 , H01L51/52
Abstract: An AMOLED doubled-sided display includes an OLED array layer that includes a plurality of top-emitting OLED units and a plurality of bottom-emitting OLED units arranged alternate with each other to form an array. Each of the top-emitting OLD units and the bottom-emitting OLED units has different thickness for respective anodes and cathodes, to realize the top-emitting characteristics of the top-emitting OLED units and the bottom-emitting characteristics of the bottom-emitting OLED units. As such, by designing an algorithm for a single IC to control image displaying, only a display panel and a control IC are sufficient to achieve double-sided displaying, and ensure an observer standing in front of the display panel will not see mirrored image or directional distorted image, as well as achieve low-cost and quality display result.
-
公开(公告)号：US20190157371A1
公开(公告)日：2019-05-23
申请号：US15505098
申请日：2016-12-27
Inventor： Shijuan Yi , Shuang Li
Abstract: The invention discloses an AMOLED doubled-sided display, with the OLED array layer comprising a plurality of top-emitting OLED units and a plurality of bottom-emitting OLED units arranged in an array, wherein the top emitting and bottom-emitting OLED units being arranged alternatingly in at least one of the horizontal direction or vertical direction; the top-emitting and bottom-emitting OLED units having different thickness for respective anodes and cathodes, to realize the top-emitting characteristics of the top-emitting OLED units and the bottom-emitting characteristics of the bottom-emitting OLED units; as such, by designing an algorithm for a single IC to control image displaying, only a display panel and a control IC are sufficient to achieve double-sided displaying, and able to ensure an observer standing in front of the display panel will not see mirrored image or directional distorted image, as well as achieve low-cost and quality display result.
-
公开(公告)号：US10242637B2
公开(公告)日：2019-03-26
申请号：US15506242
申请日：2017-02-17
Inventor： Shijuan Yi
Abstract: The invention provides a CMOS GOA circuit, which improves the NAND gate in the latch module and the inverter to connect the latch clock signal to the NAND gate in the latch module or the inverter to control the latch module to realize the input and latch of the cascade signal through the voltage change in the latch clock signal. Compared to the known technique, the present invention reduces the number of TFTs required by the latch module without affecting the normal operation of the circuit, and facilitates the implementation of the narrow border or borderless display products.
-
Patent Agency Ranking
公开(公告)号：US09947254B2
公开(公告)日：2018-04-17
申请号：US15238709
申请日：2016-08-16
Inventor： Shijuan Yi , Mang Zhao
IPC: G01R31/26 , G09G3/00 , G02F1/1345 , G09G3/36 , G02F1/1362
CPC classification number: G09G3/006 , G02F1/13452 , G02F1/13454 , G02F2001/136254 , G09G3/3648 , G09G2300/0426 , G09G2300/0819 , G09G2310/0297 , G09G2310/08 , G09G2330/12
Abstract: The present invention provides a liquid crystal display panel. The array test circuit (200) comprises a test control unit including a N type thin film transistor and a P type thin film transistor, wherein one thin film transistor is employed to be the output thin film transistor, and the other thin film transistor is employed to be the voltage stabilization thin film transistor. When the liquid crystal display panel is in the normal display state, the test control signal (ATEN) controls the output thin film transistor to be deactivated and controls the voltage stabilization thin film transistor to be activated so that the voltage difference of the gate and the source of the output thin film transistor is zero. Thus, the leakages on the data lines in the active display area (100) are consistent.
-
公开(公告)号：US09786240B2
公开(公告)日：2017-10-10
申请号：US14779016
申请日：2015-08-10
Inventor： Mang Zhao , Yong Tian , Shijuan Yi
CPC classification number: G09G3/3677 , G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2330/021 , G11C19/00 , G11C19/287
Abstract: A scan driving circuit is provided. The scan driving circuit for driving cascaded scan lines includes a scan driving circuit, a latch module, a driving-signal generation module, an output control module, a high gate voltage source, and a low level gate voltage. The scan driving circuit of the present invention conducts a driving operation for the latch module by a first cascade signal and a second cascade signal, so that a clock signal is not required to be processed with a phase inversion, and thereby the scan driving circuit has less overall power consumption.
-
公开(公告)号：US11133365B2
公开(公告)日：2021-09-28
申请号：US16819199
申请日：2020-03-16
Inventor： Shijuan Yi , Shuang Li
IPC: H01L27/32 , H01L51/52 , H01L51/56 , G09G3/3225 , H01L51/50
Abstract: An AMOLED doubled-sided display includes an OLED array layer that includes a plurality of top-emitting OLED units and a plurality of bottom-emitting OLED units arranged alternate with each other to form an array. Each of the top-emitting OLD units and the bottom-emitting OLED units has different thickness for respective anodes and cathodes, to realize the top-emitting characteristics of the top-emitting OLED units and the bottom-emitting characteristics of the bottom-emitting OLED units. As such, by designing an algorithm for a single IC to control image displaying, only a display panel and a control IC are sufficient to achieve double-sided displaying, and ensure an observer standing in front of the display panel will not see mirrored image or directional distorted image, as well as achieve low-cost and quality display result.
-
公开(公告)号：US20180151139A1
公开(公告)日：2018-05-31
申请号：US15119385
申请日：2016-05-25
Inventor： Shijuan Yi , Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/36 , G09G2310/0286 , G09G2310/0291 , G09G2310/062 , G09G2320/0223 , G09G2330/021
Abstract: The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N−2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.
-
公开(公告)号：US20180301102A1
公开(公告)日：2018-10-18
申请号：US15511016
申请日：2017-02-17
Inventor： Shijuan Yi
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3696 , G09G2300/0408 , G09G2310/0283
Abstract: The invention provides a CMOS GOA circuit, comprising a signal processing module having a first and a second TFTs, the first TFT having a gate connected to a first control signal, a source connected to an output node and a drain connected to a third node; the second TFT having a gate and a source connected to a second control signal, and a drain connected to the third node; the first and second control signals having opposite phases, the first and second control signals controlling the first and second TFTs to turn on alternatingly inputting a voltage signal of the output node or a second control signal to the third node. Compared to the known technique using NAND circuit, the invention reduces the number of TFTs required by latch module without affecting operation of the circuit, and facilitates the implementation of the ultra-narrow border or borderless display products.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.019 seconds)
