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    Programmable processing unit having multiple scopes
    2.
    发明申请
    Programmable processing unit having multiple scopes 失效
    具有多个示波器的可编程处理单元

    公开(公告)号：US20070174372A1

    公开(公告)日：2007-07-26

    申请号：US11354670

    申请日：2006-02-14

    申请人： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    发明人： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC分类号： G06F15/00

    CPC分类号： G06F21/602

    摘要： In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.

    摘要翻译： 通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。 控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联 逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合 响应一个指令。

    Programmable processing unit
    6.
    发明申请
    Programmable processing unit 有权
    可编程处理单元

    公开(公告)号：US20070192547A1

    公开(公告)日：2007-08-16

    申请号：US11354404

    申请日：2006-02-14

    申请人： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal

    发明人： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal

    IPC分类号： G06F13/00 ,  G06F12/00

    CPC分类号： G06F9/30145 ,  G06F7/5324 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/383 ,  G06F21/602 ,  G06F21/72

    摘要： In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.

    摘要翻译： 通常，在一个方面，本发明描述了一种处理单元，其包括用于存储由处理单元接收的数据的输入缓冲器，存储器，耦合到输入缓冲器和存储器的算术逻辑单元，输出缓冲器; 以及具有访问程序指令的控制存储的控制逻辑，所述控制逻辑用于处理包括将数据从所述输入缓冲器传送到所述存储器的指令的指令，以及使所述算术逻辑单元对由所述输入缓冲器提供的操作数执行操作的指令 至少一个存储器和输入缓冲器，将操作结果输出到至少一个存储器和输出缓冲器的指令。

    Cryptographic system component
    7.
    发明申请
    Cryptographic system component 审中-公开
    密码系统组件

    公开(公告)号：US20070157030A1

    公开(公告)日：2007-07-05

    申请号：US11323329

    申请日：2005-12-30

    申请人： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal

    发明人： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal

    IPC分类号： G06F12/14

    CPC分类号： G06F21/602

    摘要： In general, in aspect, the disclosure describes a system integrated on a single die that includes a first processor core to receive commands from at least one other processor core to perform at least one specified transformative operation on specified data, multiple processing units to perform transformative operations on data, a shared memory, and logic to transfer data between a one of the set of multiple processing units and the shared memory.

    摘要翻译： 一般来说，在本发明中，本公开描述了集成在单个管芯上的系统，其包括第一处理器核心，用于接收来自至少一个其他处理器核心的命令以对指定数据执行至少一个指定的变换操作，多个处理单元执行变换 对数据的操作，共享存储器和用于在多个处理单元组中的一个处理单元和共享存储器之间传送数据的逻辑。

    Configurable Exponent Fifo
    8.
    发明申请
    Configurable Exponent Fifo 有权
    可配置指数

    公开(公告)号：US20080147768A1

    公开(公告)日：2008-06-19

    申请号：US11610841

    申请日：2006-12-14

    申请人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Daniel Cutter ,  Robert P. Ottavi

    发明人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Daniel Cutter ,  Robert P. Ottavi

    IPC分类号： G06F7/38

    CPC分类号： G06F7/723

    摘要： The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开提供了一种用于执行模幂运算的系统和方法。 该方法包括将来自存储器的向量的第一字加载到第一寄存器中，并随后将第一个字从第一寄存器加载到第二寄存器。 该方法还可以包括将第二字加载到第一寄存器中并将至少一个比特从第二寄存器加载到算术逻辑单元中。 该方法还可以包括在至少一个比特上执行模幂运算以产生结果，并且至少部分地基于结果生成公开密钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    APPARATUS AND METHOD FOR EFFICIENTLY EXECUTING BOOLEAN FUNCTIONS
    9.
    发明申请
    APPARATUS AND METHOD FOR EFFICIENTLY EXECUTING BOOLEAN FUNCTIONS 审中-公开
    有效执行布尔函数的装置和方法

    公开(公告)号：US20140095845A1

    公开(公告)日：2014-04-03

    申请号：US13631807

    申请日：2012-09-28

    申请人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Kirk Yap

    发明人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Kirk Yap

    IPC分类号： G06F9/30

    摘要： An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

    摘要翻译： 描述了一种用于在流水线处理器中执行有效的布尔运算的装置和方法，其在一个实施例中不本地支持三个操作数指令。 例如，根据本发明的一个实施例的处理器包括：一组用于存储打包操作数的寄存器; 用于执行单个指令的布尔运算逻辑，其使用打包在该组寄存器中的三个或更多个源操作数，布尔运算逻辑读取至少三个源操作数，并且立即值对三个源操作数执行布尔运算，其中， 布尔操作包括：组合从三个操作数中的每一个读取的位以形成立即值的索引，该索引标识立即值内的位位置; 从识别的位置读取该位从立即值; 并将来自所识别的立即值的比特位置的比特存储在目的地寄存器中。

    RESIDUE GENERATION
    10.
    发明申请
    RESIDUE GENERATION 失效
    残留生成

    公开(公告)号：US20100153829A1

    公开(公告)日：2010-06-17

    申请号：US12336029

    申请日：2008-12-16

    申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

    发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

    IPC分类号： H03M13/09 ,  G06F7/72 ,  G06F11/10

    CPC分类号： G06F7/724 ,  H03M13/091

    摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

    摘要翻译： 在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。 操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少 是乘法的结果。 所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值 另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。