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    Programmable processing unit having multiple scopes
    4.
    发明申请
    Programmable processing unit having multiple scopes 失效
    具有多个示波器的可编程处理单元

    公开(公告)号：US20070174372A1

    公开(公告)日：2007-07-26

    申请号：US11354670

    申请日：2006-02-14

    申请人： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    发明人： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC分类号： G06F15/00

    CPC分类号： G06F21/602

    摘要： In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.

    摘要翻译： 通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。 控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联 逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合 响应一个指令。

    Hardware Accelerator
    6.
    发明申请
    Hardware Accelerator 有权
    硬件加速器

    公开(公告)号：US20080148024A1

    公开(公告)日：2008-06-19

    申请号：US11610871

    申请日：2006-12-14

    申请人： Gilbert M. Wolrich ,  William Hasenplaugh ,  Wajdi Feghali ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    发明人： Gilbert M. Wolrich ,  William Hasenplaugh ,  Wajdi Feghali ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC分类号： G06F9/302

    CPC分类号： G06F9/30014 ,  G06F21/72

    摘要： The present disclosure provides a method for instruction processing. The method may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit. The method may further include loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand. The method may also include performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register. The method may further include loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand. The method may additionally include generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开提供了一种用于指令处理的方法。 该方法可以包括从第一寄存器，第二操作数，第二寄存器和进位输入位添加第一操作数，以产生和和执行位。 该方法还可以包括将和加载到第三寄存器中，并且将进位位加载到第三寄存器的最高有效位位置以产生第三操作数。 该方法还可以包括经由移位器单元在第三操作数上执行单位移位以产生移位的操作数，并将移位的操作数加载到第四寄存器中。 该方法还可以包括将最小有效位加载到第四寄存器的最高有效位位置以产生第四操作数。 该方法可以另外包括经由第四操作数生成第一和第二操作数的最大公约数（GCD），并且至少部分地基于GCD生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Hardware accelerator
    7.
    发明授权
    Hardware accelerator 有权
    硬件加速器

    公开(公告)号：US08020142B2

    公开(公告)日：2011-09-13

    申请号：US11610871

    申请日：2006-12-14

    申请人： Gilbert M. Wolrich ,  William Hasenplaugh ,  Wajdi Feghali ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    发明人： Gilbert M. Wolrich ,  William Hasenplaugh ,  Wajdi Feghali ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F7/38

    CPC分类号： G06F9/30014 ,  G06F21/72

    摘要： A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.

    摘要翻译： 一种用于指令处理的方法可以包括从第一寄存器，第二操作数，第二寄存器和进位输入位添加第一操作数，以产生和和执行位，将所述和加载到第三寄存器并加载进位 位到第三寄存器的最高有效位位置以产生第三操作数，经由移位器单元在第三操作数上执行单位移位以产生移位操作数，并将移位的操作数加载到第四寄存器中，加载最低有效位 从总和到第四寄存器的最高有效位位置以产生第四操作数，经由第四操作数产生第一和第二操作数的最大公约数（GCD），并且至少部分地基于第二操作数生成公钥， GCD。 许多替代方案，变化和修改是可能的。

    Carry/Borrow Handling
    8.
    发明申请
    Carry/Borrow Handling 审中-公开
    携带/借款处理

    公开(公告)号：US20080148011A1

    公开(公告)日：2008-06-19

    申请号：US11610897

    申请日：2006-12-14

    申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Gunnar Gaubatz ,  Daniel Cutter ,  Wajdi Feghali ,  Kaan Yuksel ,  Erdinc Ozturk

    发明人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Gunnar Gaubatz ,  Daniel Cutter ,  Wajdi Feghali ,  Kaan Yuksel ,  Erdinc Ozturk

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3001

    摘要： The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开提供了用于执行进位/借用处理的系统和方法。 根据一个实施例的方法可以包括从第一数学运算产生具有第一进位或借位的第一结果，并将第一进位或借位以及第一指针地址存储在临时寄存器中。 该方法还可以包括从第二数学运算产生具有第二进位或借位的第二结果，并调用被配置为执行进位和借位处理的子程序。 该方法还可以包括将第一指针地址从临时寄存器复制到全局变量中。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Method for Simultaneous Modular Exponentiations
    9.
    发明申请
    Method for Simultaneous Modular Exponentiations 有权
    同时模块化指标的方法

    公开(公告)号：US20080144811A1

    公开(公告)日：2008-06-19

    申请号：US11610919

    申请日：2006-12-14

    申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Kaan Yuskel ,  Gunnar Gaubatz ,  Wajdi Feghali ,  Gilbert M. Wolrich

    发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Kaan Yuskel ,  Gunnar Gaubatz ,  Wajdi Feghali ,  Gilbert M. Wolrich

    IPC分类号： H04L9/30

    CPC分类号： G06F7/723 ,  H04L9/302

    摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开提供了一种用于执行模幂运算的方法。 该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q） ）。 该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数 第二余数（xq）升至第二素数（q）的第二私钥号（d2）。 该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。 该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。 该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    CRYPTOGRAPHIC SYSTEM, METHOD AND MULTIPLIER
    10.
    发明申请
    CRYPTOGRAPHIC SYSTEM, METHOD AND MULTIPLIER 有权
    CRYPTOGRAPHIC系统，方法和乘法器

    公开(公告)号：US20110264720A1

    公开(公告)日：2011-10-27

    申请号：US11323994

    申请日：2005-12-30

    申请人： Wajdi Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel R. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    发明人： Wajdi Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel R. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC分类号： G06F7/52 ,  G06F5/01

    CPC分类号： G06F7/5275

    摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.

    摘要翻译： 通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。 乘法器还包括耦合到逻辑的累加器。