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公开(公告)号：US5440249A
公开(公告)日：1995-08-08
申请号：US237570
申请日：1994-05-03
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K3/356113 , H03K19/00315 , H03K19/018521
摘要： A voltage level translator circuit converts an input signal referenced between first and second operating potentials to an output signal referenced between second and third operating potentials. The input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in the output stage. The input signal is delayed before driving lower cascoded transistors in the output stage. The output stage transistors are cascoded in a similar manner as the level shifting section. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translator circuit. Additional cascoded transistors may be stacked to extend the range of voltage translation. The voltage level translator circuit is applicable to sub-micron technology.
摘要翻译： 电压电平转换器电路将在第一和第二操作电位之间参考的输入信号转换为在第二和第三操作电位之间参考的输出信号。 输入信号通过级联转换晶体管并由串联逆变器锁存，以驱动输出级的上级串联晶体管。 在输出级驱动较低级联的晶体管之前，输入信号被延迟。 输出级晶体管以与电平移位部分类似的方式被级联。 输入信号的逻辑状态确定输出级中的上级联型晶体管或下级联型晶体管是否被激活，以设置电压电平转换器电路的输出信号的逻辑状态。 可以堆叠附加的级联三极管以延长电压转换的范围。 电压转换器电路适用于亚微米技术。
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公开(公告)号：US4948991A
公开(公告)日：1990-08-14
申请号：US266613
申请日：1988-11-03
IPC分类号： H03K19/01 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K19/0136
摘要： An ECL transient driver discharges a capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load. A pull-up transistor is coupled to an output terminal for selectively supplying a voltage thereto in response to a first signal from a logic circuit. A pull-down transistor is coupled to the output terminal for selectively sinking a current therefrom in response to a second signal. A comparator circuit is coupled to the pull-down transistor, the logic circuit, and the output terminal, for selectively providing the second signal in response to the first signal and an output voltage on the output terminal.
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公开(公告)号：US5120998A
公开(公告)日：1992-06-09
申请号：US664896
申请日：1991-03-04
IPC分类号： H03K19/086 , H03F3/72 , H03K19/0175 , H03K19/018 , H04L25/08
CPC分类号： H04L25/08 , H03K19/01825
摘要： A source terminated transmission line driver circuit having an output coupled to a transmission line through a resistor is provided. The driver circuit has a gate circuit for providing first and second signals and a pulse generator circuit responsive to the second signal of the gate circuit for providing a pulse current at an output when the second signal is switching from a first logic state to a second logic state and for otherwise providing a quiescent current at the output. The driver circuit also has a first circuit responsive to the first output signal of the gate circuit for sourcing current to the output of the source terminated transmission line driver circuit, the first circuit being responsive to the second output signal of the gate circuit for sinking an adjustable current at the output of the source terminated transmission line driver circuit. The first circuit has a first transistor having a collector, a base and an emitter, the emitter being coupled to the output of the source terminated transmission line driver circuit, the base being coupled to receive the first signal of the gate circuit, and the collector being coupled to the first supply voltage terminal, a second transistor having a collector, a base and an emitter, the emitter of the second transistor being coupled to the output of the source terminated transmission line driver circuit, the base of the second transistor being coupled to the output of the pulse generator circuit, the collector being coupled to a second supply voltage terminal, a third transistor having a collector, a base and an emitter, the collector of the third transistor being coupled to the first supply voltage terminal, the base of the third transistor being coupled to the base of the first transistor, and a fourth transistor having a collector, a base and an emitter, the collector and base of the fourth transistor being coupled to the emitter of the third transitor, the emitter of the fourth transistor being coupled to the base of the second transistor.
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公开(公告)号：US20100150275A1
公开(公告)日：2010-06-17
申请号：US12333846
申请日：2008-12-12
申请人： Noshir Dubash , Siva Bonasu , Peter Naji , Douglas W. Schucker
发明人： Noshir Dubash , Siva Bonasu , Peter Naji , Douglas W. Schucker
IPC分类号： H04L27/06
CPC分类号： H04B1/001 , H04B1/0014
摘要： Systems and methods for mitigating multipath signals in a receiver are provided. In this regard, a representative system, among others, includes a radio frequency (RF) front-end and at least one analog-to-digital converter (ADC). The RF front-end receives FM signals and down-converts the received frequency signals to intermediate frequency (IF) signals. The analog-to-digital converter (ADC) receives the intermediate frequency signals and digitizes multiple FM channels around a desired FM channel associated with the down-converted signals. The system further includes multiple sets of digital processing components that are configured to simultaneously receive and process the digitized multiple channels. The multiple sets of digital processing components include at least two parallel channel selection and demodulation paths in which the respective digitized multiple channels are processed therethrough.
摘要翻译： 提供了用于减轻接收机中的多径信号的系统和方法。 在这方面，代表性系统包括射频（RF）前端和至少一个模拟 - 数字转换器（ADC）。 RF前端接收FM信号并将接收的频率信号下变频为中频（IF）信号。 模数转换器（ADC）接收中频信号，并围绕与下变频信号相关联的期望的FM信道数字化多个FM信道。 该系统还包括多组数字处理组件，其被配置为同时接收和处理数字化的多个通道。 多组数字处理组件包括至少两个并行通道选择和解调路径，其中相应的数字化多个通道被处理。
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公开(公告)号：US4616146A
公开(公告)日：1986-10-07
申请号：US647216
申请日：1984-09-04
申请人： Shi-Chuan Lee , Douglas W. Schucker
发明人： Shi-Chuan Lee , Douglas W. Schucker
IPC分类号： H03K19/013 , H03K19/0944 , H03K19/01 , H03K19/082 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/0136
摘要： A BI-CMOS circuit is provided wherein an output terminal is coupled between an upper and lower NPN push-pull transistor. This provides high current drive capability along with no d.c. power dissipation. A P-channel device has a source and a drain connected to the collector and base, respectively, of the upper NPN transistor. An N-channel device has a source and drain connected to the base and collector, respectively, of the lower NPN transistor. The gates of the P-channel and N-channel devices are connected to an input terminal and provide a high impedance thereat. Additional N-channel devices are coupled between the bases of the upper and lower NPN transistors and a supply voltage terminal for improving the switching speed of the output signal.
摘要翻译： 提供了一种BI-CMOS电路，其中输出端耦合在上NPN推挽晶体管和下NPN推挽晶体管之间。 这提供高电流驱动能力以及无直流电流。 功耗。 P沟道器件的源极和漏极分别连接到上部NPN晶体管的集电极和基极。 N沟道器件的源极和漏极分别连接到下部NPN晶体管的基极和集电极。 P沟道和N沟道器件的栅极连接到输入端并提供高阻抗。 附加的N沟道器件耦合在上，下NPN晶体管的基极和用于提高输出信号的开关速度的电源电压端子之间。
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6.发明授权Simulation of sequential circuits for calculating timing characteristics to design/manufacture a logic network 失效用于计算定时特性以设计/制造逻辑网络的时序电路的仿真
公开(公告)号：US5461575A
公开(公告)日：1995-10-24
申请号：US203128
申请日：1994-02-28
申请人： Douglas W. Schucker , Greg Djaja , Lee Mah
发明人： Douglas W. Schucker , Greg Djaja , Lee Mah
CPC分类号： G01R31/3016 , G06F17/5022
摘要： A method for obtaining characterization of timing parameters of a sequential circuit includes inputting predetermined data sequences to the sequential circuit. The sequential circuit is then simulated in response to the predetermined data sequences, and signals appearing at internal nodes of the sequential circuit are observed with respect to time. A plurality of timing parameters of the sequential circuit can then be calculated by using the values of the signals at the internal nodes.
摘要翻译： 用于获得顺序电路的定时参数的表征的方法包括将预定数据序列输入到顺序电路。 然后响应于预定数据序列模拟顺序电路，并且相对于时间观察出现在顺序电路的内部节点处的信号。 然后可以通过使用内部节点处的信号的值来计算顺序电路的多个定时参数。
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7.发明申请公开(公告)号：US20100151786A1
公开(公告)日：2010-06-17
申请号：US12332590
申请日：2008-12-11
IPC分类号： H04B7/00
摘要： Systems and methods for channel pairing a transmitter and a receiver are provided. In this regard, a representative method, among others, includes selecting a channel in a radio frequency (RF) band; transmitting a carrier and alert tone on the selected channel in the RF band; responsive to detecting the transmitted carrier and alert tone, demodulating the carrier and alert tone on the selected channel in the RF band and producing the demodulated alert tone; and responsive to detecting the produced alert tone, using the selected channel to establish a wireless link between the transmitter and receiver.
摘要翻译： 提供了用于发射机和接收机的信道配对的系统和方法。 在这方面，代表性的方法包括选择射频（RF）频带中的频道; 在RF频段的所选频道上发送载波和提示音; 响应于检测所发送的载波和报警音，解调在RF频带中所选频道上的载波和提示音，并产生解调的提示音; 并且响应于检测所产生的警报音，使用所选择的信道在发射机和接收机之间建立无线链路。
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公开(公告)号：US5359535A
公开(公告)日：1994-10-25
申请号：US878062
申请日：1992-05-04
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method for optimization of delay times in a digital circuit. The method comprises selecting a logic gate (12), and constructing a model (35) which predicts the delay time (27) of the logic gate (12). Varying the parameters which control the model to more accurately predict the delay time (48). Summing the delay time (48) due to each logic gate (12) which comprises the signal path. Repeating the method for each signal path within the digital circuit until all signal paths are computed. Modifying the digital circuit based on the calculated delay times (48) so as to better satisfy a predetermined measurement criteria.
摘要翻译： 一种用于优化数字电路中的延迟时间的方法。 该方法包括选择逻辑门（12），以及构建预测逻辑门（12）的延迟时间（27）的模型（35）。 改变控制模型的参数以更准确地预测延迟时间（48）。 将由于包括信号路径的每个逻辑门（12）引起的延迟时间（48）相加。 重复数字电路内每个信号路径的方法，直到计算所有信号路径。 基于所计算的延迟时间（48）修改数字电路，以便更好地满足预定的测量标准。
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9.发明授权Firm function block for a programmable block architected heterogeneous integrated circuit 失效用于可编程块架构异构集成电路的固件功能块
公开(公告)号：US5283753A
公开(公告)日：1994-02-01
申请号：US735738
申请日：1991-07-25
CPC分类号： H01L27/0207 , G06F17/5068
摘要： A block architected integrated circuit having a predetermined power and signal grid structures is provided. The integrated circuit includes a plurality of function blocks such as firm function blocks, standard cell logic blocks, and gate array logic blocks which are all designed according to the power and signal grid structures of the integrated circuit and from standard library elements of the base cell array. These function blocks have full floating capability with respect to the granularity of the power and signal grid structures.The integrated circuit also includes one or more hard function blocks which are not designed according to the power or signal grid structures of the integrated circuit. Further, the integrated circuit may also include one or more blocks which are designed from a different technology than the base cell array of the integrated circuit and, thus are also not designed according to the power or signal grid structures of the integrated circuit. As a result, these blocks must be adapted to readily fit within the power and signal grid structures of the integrated circuit. However, once adapted, these blocks also have full floating capability with respect to the granularity of the power and signal grid structures.
摘要翻译： 提供具有预定功率和信号格栅结构的块结构集成电路。 集成电路包括多个功能块，例如固定功能块，标准单元逻辑块和门阵列逻辑块，它们都是根据集成电路的功率和信号网格结构以及基站的标准库元件而设计的 数组。 这些功能块相对于功率和信号格栅结构的粒度具有完全的浮动能力。 集成电路还包括不根据集成电路的功率或信号网格结构设计的一个或多个硬功能块。 此外，集成电路还可以包括由与集成电路的基本单元阵列不同的技术设计的一个或多个块，并且因此也不根据集成电路的功率或信号网格结构设计。 结果，这些块必须适于容易地适应集成电路的功率和信号格栅结构。 然而，一旦适应，这些块对于功率和信号格栅结构的粒度也具有完全的浮动能力。
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公开(公告)号：US5155390A
公开(公告)日：1992-10-13
申请号：US735744
申请日：1991-07-25
IPC分类号： H01L27/02
CPC分类号： H01L27/0207
摘要： A block architected integrated circuit having predetermined power and signal grid structures is provided. The integrated circuit includes a plurality of function blocks such as firm function blocks, standard cell logic blocks, and gate array logic blocks which are all designed according to the power and signal grid structures of the integrated circuit and from standard library elements of the base cell array. These function blocks have full floating capability with respect to the granularity of the power and signal grid structures.The integrated circuit also includes one or more hard function blocks which are not designed according to the power or signal grid structures of the integrated circuit. Further, the integrated circuit may also include one or more blocks which are designed from a different technology than the base cell array of the integrated circuit and, thus are also not designed according to the power or signal grid structures of the integrated circuit. As a result, these blocks must be adapted to readily fit within the power and signal grid structures of the integrated circuit. However, once adapted, these blocks also have full floating capability with respect to the granularity of the power and signal grid structures.
摘要翻译： 提供了一种具有预定功率和信号格栅结构的块结构集成电路。 集成电路包括多个功能块，例如固定功能块，标准单元逻辑块和门阵列逻辑块，它们都是根据集成电路的功率和信号网格结构以及基站的标准库元件而设计的 数组。 这些功能块相对于功率和信号格栅结构的粒度具有完全的浮动能力。 集成电路还包括不根据集成电路的功率或信号网格结构设计的一个或多个硬功能块。 此外，集成电路还可以包括由与集成电路的基本单元阵列不同的技术设计的一个或多个块，并且因此也不根据集成电路的功率或信号网格结构设计。 结果，这些块必须适于容易地适应集成电路的功率和信号格栅结构。 然而，一旦适应，这些块对于功率和信号格栅结构的粒度也具有完全的浮动能力。
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