公开(公告)号：US06106565A

公开(公告)日：2000-08-22

申请号：US807162

申请日：1997-02-27

申请人： Warren Stapleton ,  Keith R. Shakel ,  Fred C. Jair ,  Jennifer B. Pencis ,  Mrityunjay R. Hiremath

发明人： Warren Stapleton ,  Keith R. Shakel ,  Fred C. Jair ,  Jennifer B. Pencis ,  Mrityunjay R. Hiremath

IPC分类号： G06F9/455 ,  G06F15/173 ,  G06F16/16

CPC分类号： G06F9/455

摘要： A development system includes two processors which can each act as the central processing unit of the development system. Control is passed between the processors via a system management mode (SMM) interrupt under the X86 architecture. In one embodiment, one of the processor is a processor to be emulated and the other processor is an emulating processor. Since the emulating processor runs at a much slower clock speed than the emulated processor, an application program can be run by the emulating processor until a region of interest is reached. The control of the application program can then be transferred by the SMM interrupt to the emulated processor. This arrangement allows a new compatible microprocessor to be efficiently developed using a hardware emulation system.

摘要翻译： 开发系统包括两个处理器，每个处理器可以充当开发系统的中央处理单元。 控制通过X86架构下的系统管理模式（SMM）中断在处理器之间传递。 在一个实施例中，处理器之一是待仿真的处理器，而另一处理器是仿真处理器。 由于仿真处理器以比仿真处理器更慢的时钟速度运行，所以仿真处理器可以运行应用程序，直到达到感兴趣的区域。 然后，应用程序的控制可以通过SMM中断传送到仿真处理器。 这种布置允许使用硬件仿真系统有效地开发新的兼容微处理器。