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公开(公告)号:US06106565A
公开(公告)日:2000-08-22
申请号:US807162
申请日:1997-02-27
申请人: Warren Stapleton , Keith R. Shakel , Fred C. Jair , Jennifer B. Pencis , Mrityunjay R. Hiremath
发明人: Warren Stapleton , Keith R. Shakel , Fred C. Jair , Jennifer B. Pencis , Mrityunjay R. Hiremath
IPC分类号: G06F9/455 , G06F15/173 , G06F16/16
CPC分类号: G06F9/455
摘要: A development system includes two processors which can each act as the central processing unit of the development system. Control is passed between the processors via a system management mode (SMM) interrupt under the X86 architecture. In one embodiment, one of the processor is a processor to be emulated and the other processor is an emulating processor. Since the emulating processor runs at a much slower clock speed than the emulated processor, an application program can be run by the emulating processor until a region of interest is reached. The control of the application program can then be transferred by the SMM interrupt to the emulated processor. This arrangement allows a new compatible microprocessor to be efficiently developed using a hardware emulation system.
摘要翻译: 开发系统包括两个处理器,每个处理器可以充当开发系统的中央处理单元。 控制通过X86架构下的系统管理模式(SMM)中断在处理器之间传递。 在一个实施例中,处理器之一是待仿真的处理器,而另一处理器是仿真处理器。 由于仿真处理器以比仿真处理器更慢的时钟速度运行,所以仿真处理器可以运行应用程序,直到达到感兴趣的区域。 然后,应用程序的控制可以通过SMM中断传送到仿真处理器。 这种布置允许使用硬件仿真系统有效地开发新的兼容微处理器。
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公开(公告)号:US5793941A
公开(公告)日:1998-08-11
申请号:US566876
申请日:1995-12-04
申请人: Jennifer B. Pencis , Atish Ghosh
发明人: Jennifer B. Pencis , Atish Ghosh
CPC分类号: G06F12/0897 , G06F11/22
摘要: A primary cache test system is supplied using a secondary cache that closely matches specifications of the primary cache. Coherency is maintained between the primary and secondary caches using inclusion by a write-once protocol. The test system includes software which suspends cache operations on receipt of an error signal from a secondary cache controller or by periodically pausing cache operations for cache operation monitoring. During suspension of cache operations, the software verifies the states of the primary cache against the states and data within the secondary cache. Signals on cache hit and hit-modified pins that are available on the microprocessor integrated circuit are monitored to detect various error conditions. Error analysis includes detection of invalid hits to the primary cache, incorrectly modified lines in the primary cache and misses to the primary cache that should be hits.
摘要翻译: 使用与主缓存严格匹配的二级缓存提供主缓存测试系统。 通过一次写入协议使用包含在一级和二级缓存之间维持一致性。 测试系统包括在接收到来自二级高速缓存控制器的错误信号时暂停高速缓存操作的软件,或者通过周期性地暂停用于高速缓存操作监视的缓存操作。 在暂停高速缓存操作期间,软件会根据二级缓存中的状态和数据来验证主缓存的状态。 监视微处理器集成电路上可用的高速缓存命中和命中修正引脚上的信号,以检测各种错误状况。 错误分析包括检测到主缓存中的无效命中,主缓存中未正确修改的行,以及未命中的主缓存。
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公开(公告)号:US5598556A
公开(公告)日:1997-01-28
申请号:US568849
申请日:1995-12-07
申请人: Atish Ghosh , Jennifer B. Pencis
发明人: Atish Ghosh , Jennifer B. Pencis
CPC分类号: G06F11/3428 , G06F1/04 , H03K5/156 , G06F11/3419 , G06F2201/88
摘要: A conditional wait state generator is interposed into the timing circuitry of a processor. The conditional wait state generator provides for analysis of a selected cycle type and for selection of the latency or number of wait states that is imposed during processor execution for that selected cycle type. In accordance with another aspect of the conditional wait state generator, a method of analyzing processor performance under specific operating conditions involves selection of a particular cycle type for testing and selection of a number of wait states that is imposed on processor operations for the selected cycle type and not for other cycle types. A conditional wait state generator is interposed into the timing circuitry of a processor and thereby imposes the selected conditions on the processor for analysis.
摘要翻译: 条件等待状态发生器插入到处理器的定时电路中。 条件等待状态发生器提供对所选择的周期类型的分析,并且用于选择在该选择的周期类型的处理器执行期间施加的等待时间或等待状态数。 根据条件等待状态发生器的另一方面,在特定操作条件下分析处理器性能的方法涉及选择用于测试和选择施加在所选择的周期类型的处理器操作上的等待状态的数量的特定周期类型 而不适用于其他循环类型。 条件等待状态发生器被插入到处理器的定时电路中,从而将所选择的条件施加在处理器上用于分析。
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公开(公告)号:US5619468A
公开(公告)日:1997-04-08
申请号:US568848
申请日:1995-12-07
申请人: Atish Ghosh , Jennifer B. Pencis
发明人: Atish Ghosh , Jennifer B. Pencis
IPC分类号: G11C11/406 , G06F12/02
CPC分类号: G11C11/406
摘要: A timing refresh circuit refreshes a timed circuit in a functionally equivalent manner, whether the timing refresh circuit is operated at a high frequency or a low frequency. The two-stage timing refresh circuit includes a counter and combinational logic, in combination, connected between a refresh timing signal generator and a control circuit. The counter is incremented for each refresh timing signal and decremented for each refresh cycle realized by the control circuit. The combinational logic converts the counter count to a refresh signal by generating a refresh request to the control circuit whenever a count is pending in the counter.
摘要翻译: 定时刷新电路以功能等效的方式刷新定时电路,无论定时刷新电路是以高频还是低频工作。 两级定时刷新电路包括组合地连接在刷新定时信号发生器和控制电路之间的计数器和组合逻辑。 对于每个刷新定时信号,计数器递增,并且由控制电路实现的每个刷新周期递减计数器。 组合逻辑将计数器计数转换为刷新信号,只要计数器中的计数处于等待状态,就向控制电路生成刷新请求。
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