公开(公告)号：US5580701A

公开(公告)日：1996-12-03

申请号：US261057

申请日：1994-06-16

申请人： Water Lur ,  Po-Wen Yen

发明人： Water Lur ,  Po-Wen Yen

IPC分类号： G03F7/09 ,  H01L21/00

CPC分类号： G03F7/091 ,  Y10S430/151 ,  Y10S438/95 ,  Y10S438/952

摘要： A method is disclosed which eliminates standing waves in the photoresist layer of VLSI devices. A layer of anti-reflecting material is deposited between the photoresist and its underlying poly layer. This anti-reflecting layer is formed with an appropriate thickness and index of refraction so that none of the lithographic light incident on the photoresist is reflected back from the underlying layer. This eliminates the interference between incident and reflected light in the photoresist, thus preventing the occurrence of standing waves.

摘要翻译： 公开了消除VLSI器件的光致抗蚀剂层中的驻波的方法。 一层抗反射材料沉积在光致抗蚀剂及其下面的多层之间。 该抗反射层形成有适当的厚度和折射率，使得入射到光致抗蚀剂上的光刻光不会从底层反射回来。 这消除了光致抗蚀剂中的入射光和反射光之间的干扰，从而防止驻波的发生。

公开(公告)号：US5445989A

公开(公告)日：1995-08-29

申请号：US294371

申请日：1994-08-23

申请人： Water Lur ,  Po-Wen Yen

发明人： Water Lur ,  Po-Wen Yen

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/316 ,  H01L21/76229

摘要： A new method of forming device isolation regions on a silicon substrate is provided. This method comprises the following steps: a pad oxide layer is formed on the silicon substrate; a silicon nitride layer is formed on the pad oxide layer; portions of the silicon nitride and pad oxide layers not covered by a mask pattern are etched through and into the silicon substrate so as to provide a plurality of wide and narrow trenches within the silicon substrate that will form the device isolation regions; silicon nitride spacers are formed on the sidewalls of the trenches; a first field oxide layer is grown on bottoms of the trenches by using thermal oxidation wherein a thin oxide layer is also formed on the silicon nitride layer; the thin oxide layer, silicon nitride layer, silicon nitride spacers and pad oxide layer are removed, respectively; and a second field oxide layer is formed on the first field oxide layer by using liquid phase deposition so as to fill all of the trenches.

摘要翻译： 提供了一种在硅衬底上形成器件隔离区的新方法。 该方法包括以下步骤：在硅衬底上形成衬垫氧化层; 在衬垫氧化物层上形成氮化硅层; 未被掩模图案覆盖的氮化硅和衬垫氧化物层的部分被蚀刻穿过硅衬底并在硅衬底内提供将形成器件隔离区的硅衬底内的多个宽而窄的沟槽; 氮化硅间隔物形成在沟槽的侧壁上; 通过使用热氧化在沟槽的底部生长第一场氧化物层，其中在氮化硅层上也形成薄的氧化物层; 分别去除薄氧化物层，氮化硅层，氮化硅间隔物和衬垫氧化物层; 并且通过使用液相沉积在第一场氧化物层上形成第二场氧化物层，以填充所有的沟槽。

公开(公告)号：US5773082A

公开(公告)日：1998-06-30

申请号：US783906

申请日：1997-01-16

申请人： Chi-Fa Ku ,  Chih-Hsing Hsin ,  Po-Wen Yen

发明人： Chi-Fa Ku ,  Chih-Hsing Hsin ,  Po-Wen Yen

IPC分类号： B05D1/00 ,  G03F7/16 ,  B05D3/12

CPC分类号： G03F7/162 ,  B05D1/005 ,  G03F7/168

摘要： A method for applying photoresist on a wafer is disclosed. The method comprises: lowering the temperature of the photoresist, and dispensing the photoresist on a portion of the wafer, where the wafer is supported by a spinner chuck and is rotated at a low speed. Thereafter, spreading the photoresist on the wafer by rotating the wafer at a high speed. Finally, planarizing the photoresist by rotating the wafer at a medium speed greater than or equal to the low speed in the dispensing step and less than or equal to the high speed in the spreading step.

摘要翻译： 公开了一种在晶片上施加光致抗蚀剂的方法。 该方法包括：降低光致抗蚀剂的温度，并将光致抗蚀剂分配在晶片的一部分上，其中晶片由旋转卡盘支撑并以低速旋转。 此后，通过高速旋转晶片将光致抗蚀剂铺展在晶片上。 最后，通过在分配步骤中以大于或等于低速的中等速度旋转晶片并且在扩展步骤中小于或等于高速来平坦化光致抗蚀剂。

公开(公告)号：US5637186A

公开(公告)日：1997-06-10

申请号：US561875

申请日：1995-11-22

申请人： Chih-Chiang Liu ,  Po-Wen Yen ,  Hsi-Hsin Hong

发明人： Chih-Chiang Liu ,  Po-Wen Yen ,  Hsi-Hsin Hong

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L22/34

摘要： A process and a monitor structure to measure semiconductor device dimensions, especially contact and via hole dimensions, and proximity effects. The monitor has structures and layers which match the thickness and configuration of the product devices and allow measurement of step heights and proximity measurements. The monitor pattern includes an alignment region for use with automeasurement equipment. Measurements of openings are performed on the monitor at various points during the fabrication process.

摘要翻译： 测量半导体器件尺寸，特别是接触孔和通孔尺寸以及邻近效应的工艺和监测结构。 显示器具有与产品设备的厚度和配置匹配的结构和层，并允许测量台阶高度和接近度测量。 监视器图案包括用于与自动测量设备一起使用的对准区域。 在制造过程中在各个点处对显示器进行开口的测量。

公开(公告)号：US5413963A

公开(公告)日：1995-05-09

申请号：US289648

申请日：1994-08-12

申请人： Po-Wen Yen ,  Army Chung ,  Her-Song Liaw

发明人： Po-Wen Yen ,  Army Chung ,  Her-Song Liaw

IPC分类号： H01L21/312 ,  H01L21/28 ,  H01L21/318

CPC分类号： H01L21/3121

摘要： A method of forming a metallurgy system on a semiconductor substrate is provided. A first conformal layer of SiO.sub.2 is deposited on the substrate using plasma enhanced chemical vapor deposition (PECVD) techniques. Subsequently a non-conformal organic layer is deposited by spin-on-glass (SOG) techniques over the first layer, and heated to smoothen the surface. The organic SOG deposited layer is then subjected to a N.sub.2 plasma environment and a second conformal layer of SiO.sub.2 is deposited, and then vias etched through the layers. The resist layer used to define vias is removed by an O.sub.2 plasma and the device metallurgy completed.

摘要翻译： 提供了一种在半导体衬底上形成冶金系统的方法。 使用等离子体增强化学气相沉积（PECVD）技术在衬底上沉积第一保形层SiO 2。 随后，通过旋涂玻璃（SOG）技术在第一层上沉积非保形有机层，并加热以使表面光滑。 然后将有机SOG沉积层进行N2等离子体环境，并沉积SiO 2的第二共形层，然后通过层蚀刻通孔。 用于限定通孔的抗蚀剂层通过O 2等离子体去除，并且器件冶金完成。