Abstract:
An embodiment of the invention provides a touch panel, which includes a substrate, a lower conductive layer overlaying the substrate, an insulating layer overlaying the lower conductive layer, and an upper conductive layer overlaying the insulating layer. The lower conductive layer includes a plurality of first conductive patterns including a plurality of first electrodes and a plurality of first dummy patterns, wherein the first dummy patterns are electrically insulated from the first conductive patterns. The upper conductive layer includes a plurality of second conductive patterns including a plurality of second electrodes respectively overlapping the first dummy patterns and a plurality of second dummy patterns, wherein the second dummy patterns are electrically insulated from the second conductive patterns and respectively overlapping the first electrodes.
Abstract:
The present invention relates to a projecting capacitive touch sensing device, display panel, and image display system. The projecting capacitive touch sensing comprises an array of a plurality of sensing units, each sensing unit including: a first electrode made of a sensing material, at least one second electrode made of a sensing material and being disposed around the peripheral of the first electrode, at least one first sensing axis electrically connected to the first electrode, and at least one second sensing axis electrically connected to the second electrodes. The first electrode is quadrangle, while the second electrodes are triangular-shaped. The first electrode and the plurality of second electrodes are arranged to form a rectangular, and a non-sensing area is defined between the first electrode and the second electrodes.
Abstract:
An image displaying system is provided, in which a touch panel comprises a transparent substrate with a first surface and a second surface opposite to the first surface, a black matrix, a protection layer, at least one first transparent electrode, a planarization layer, a color filter and a common electrode. The black matrix is disposed on the second surface to define at least one transparent region. The protection layer is disposed on the black matrix and the transparent region, and the first transparent electrode is disposed on the protection layer and within the transparent region, wherein the first transparent electrode, the transparent substrate and an external electrode form a touch sensing capacitor. The planarization layer is disposed on the protection layer and the first transparent electrode, the color filter is disposed on the planarization layer, and the common electrode is disposed on the planarization layer and covering the color filter.
Abstract:
An image displaying system is provided, in which a touch panel comprises a transparent substrate with a first surface and a second surface opposite to the first surface, a black matrix, a protection layer, at least one first transparent electrode, a planarization layer, a color filter and a common electrode. The black matrix is disposed on the second surface to define at least one transparent region. The protection layer is disposed on the black matrix and the transparent region, and the first transparent electrode is disposed on the protection layer and within the transparent region, wherein the first transparent electrode, the transparent substrate and an external electrode form a touch sensing capacitor. The planarization layer is disposed on the protection layer and the first transparent electrode, the color filter is disposed on the planarization layer, and the common electrode is disposed on the planarization layer and covering the color filter.
Abstract:
A display may have a thin-film-transistor layer with a substrate layer. A layer of dielectric may be formed on the substrate layer and may have an upper surface and a lower surface. The thin-film-transistor layer may include an array of display pixels. Data lines and gate lines may provide signals to the display pixels. Gate driver circuitry in an inactive peripheral portion of the display may include a gate driver circuit for each gate line. The gate driver circuits may include thin-film transistors that are formed on the upper surface of the layer of dielectric. Signal lines such as a gate low line, a gate routing line coupled between the gate driver circuits, and a common electrode line may be formed from two or more layers of metal to reduce their widths or may be embedded within the dielectric layer between the upper and lower surfaces under the thin-film transistors.
Abstract:
An illumination device includes a transparent substrate and multiple first metal lines. The transparent substrate includes an emitting area and a peripheral area and the emitting area includes multiple sub-emitting areas. The first metal lines are disposed on the transparent substrate, each first metal line has an end connected to a corresponding one of the sub-emitting areas and an opposite end connected to the peripheral area. Each sub-emitting area includes an insulating layer, a second metal line and an OLED layer. The second metal line is disposed between the transparent substrate and the OLED layer, the insulating layer is between the first metal lines and the second metal line, each first metal line is overlapped with the second metal line in vertical projection. One of the first metal lines, which is connected to a first one of the sub-emitting areas, passes through a second one of the sub-emitting areas.
Abstract:
An electronic illuminating device includes an illuminating area, a routing area and a control area. The illuminating area includes multiple light-emitting blocks and multiple illuminating area power-supply lines. Each the light-emitting block employs at least one light-emitting element as light source, and further is electrically coupled to a corresponding one of the illuminating area power-supply lines. The routing area includes multiple routing area power-supply lines, and each the routing area power-supply line is electrically coupled to a corresponding one of the illuminating area power-supply lines. The control area provides powers to the routing area power-supply lines. A width of at least one of the illuminating area power-supply lines and the corresponding routing area power-supply line or a length of at least one of the routing area power-supply lines is adjusted, such that differences among resistances between the light-emitting blocks and the control area are within 20%.
Abstract:
A gate signal adjustment circuit for a display is disclosed. The gate signal adjustment circuit can adjust a transition time of a gate signal used to drive data displaying. The adjustment can be to either speed up or slow down the transition time according to the requirements of the display. In an example, the gate signal adjustment circuit can include multiple transistors, where a first set of the transistors outputs the gate signal and a second set of the transistors outputs an adjustment to the gate signal. The second set of transistors can be the same or different sizes depending on the desirable number of adjustment options. The circuit can also include a control line coupled to the second set of transistors to control the adjustment output. Gate signal adjustment can reduce crosstalk in the display.
Abstract:
A system for displaying images including a touch display panel is provided. The touch display panel includes a first substrate. An electrode array is disposed on the first substrate, and the electrode array includes a first touch area. A first common electrode layer is disposed on the electrode array. A first dielectric layer is disposed between the electrode array and the first common electrode layer.
Abstract:
Disclosed embodiments relate to signal routings for use in a display device. The display device may include a liquid crystal display (LCD) panel having multiple pixels arranged in rows and columns. Each of the pixels includes a pixel electrode and a thin-film transistor (TFT). The LCD may include a conductive signal routing portion having a first metallic layer, a second metallic layer formed directly on the first metallic layer, and a third metallic layer formed directly on the second metallic layer. The first metallic layer may include a contact terminal. The second metallic layer when combined with the third metallic layers may decrease the resistance of the third metallic layer.