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    Protection structure for metal-oxide-metal capacitor
    1.
    发明授权
    Protection structure for metal-oxide-metal capacitor 有权
    金属氧化物金属电容器的保护结构

    公开(公告)号：US08971014B2

    公开(公告)日：2015-03-03

    申请号：US12984731

    申请日：2011-01-05

    申请人： Wei-Chun Hua ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao ,  Jye-Yen Cheng ,  Hua-Chou Tseng

    发明人： Wei-Chun Hua ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao ,  Jye-Yen Cheng ,  Hua-Chou Tseng

    IPC分类号： H01G4/228 ,  H01L49/02 ,  H01L23/522

    CPC分类号： H01G4/005 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

    摘要： A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.

    摘要翻译： 电容器结构包括第一和第二组电极和多个线插头。 第一组电极具有形成在多个金属化层中的第一金属化层中的第一电极和第二电极，其中第一电极和第二电极被绝缘材料分开。 第二组电极具有形成在多个金属化层之间的第二金属化层中的第三电极和第四电极，其中第三电极和第四电极被绝缘材料隔开。 线插头将第二组电极连接到第一组电极。

    Contact structure for reducing gate resistance and method of making the same
    2.
    发明授权
    Contact structure for reducing gate resistance and method of making the same 有权
    用于降低栅极电阻的接触结构及其制造方法

    公开(公告)号：US08765600B2

    公开(公告)日：2014-07-01

    申请号：US12913982

    申请日：2010-10-28

    申请人： Chung-Long Chang ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Hua-Chao Tseng ,  Jye-Yen Cheng ,  Harry-Hak-Lay Chuang

    发明人： Chung-Long Chang ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Hua-Chao Tseng ,  Jye-Yen Cheng ,  Harry-Hak-Lay Chuang

    IPC分类号： H01L21/4763 ,  H01L29/76

    CPC分类号： H01L21/76838 ,  H01L21/76807 ,  H01L21/76816 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material.

    摘要翻译： 一种具有栅极的半导体器件，具有与栅极相邻的源极/漏极（S / D）区域的衬底。 第一介电层覆盖栅极和S / D区域，第一介电层在S / D区域上具有第一接触孔，第一接触插塞由第一材料形成，第一接触插塞连接到相应的S / D区域。 第二电介质层覆盖第一电介质层和第一接触插塞。 形成在第一和第二电介质层中的第二接触孔填充有由第二材料形成的第二接触插塞。 第二接触插塞耦合到形成在第二介电层中的栅极和互连结构，互连结构耦合到第一接触插塞。 第二材料与第一材料不同，第二材料的电阻低于第一材料的电阻。

    Interdigitated capacitive structure for an integrated circuit
    3.
    发明授权
    Interdigitated capacitive structure for an integrated circuit 有权
    用于集成电路的交叉电容结构

    公开(公告)号：US08169014B2

    公开(公告)日：2012-05-01

    申请号：US11328502

    申请日：2006-01-09

    申请人： Yueh-You Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    发明人： Yueh-You Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    IPC分类号： H01L29/92

    CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.

    摘要翻译： 用于集成电路的改进的互指电容结构的系统和方法。 优选实施例包括基本上平行的叉指序列序列的第一层，每个条带具有第一极性或第二极性，该序列在第一极性的条带和第二极性的条之间交替。 第一介电层沉积在第一层条带的每条上。 基本上交错的延伸条的序列的第一延伸层沉积在第一介电层上，每个延伸条沉积在具有相反极性的第一层的条上。 通孔的第一序列耦合到第一延伸层，每个通孔沉积在相同极性的延伸条上。 基本上平行的叉指序列序列的第二层可以耦合到第一序列通孔。

    Capacitor Pairs with Improved Mismatch Performance
    4.
    发明申请
    Capacitor Pairs with Improved Mismatch Performance 有权
    具有改进的不匹配性能的电容对

    公开(公告)号：US20090212392A1

    公开(公告)日：2009-08-27

    申请号：US12463949

    申请日：2009-05-11

    申请人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    发明人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    IPC分类号： H01L29/92

    CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.

    摘要翻译： 半导体器件包括：第一电容器，包括彼此互连的多个第一单位电容器，每个具有第一单位电容; 以及包括彼此互连的多个第二单位电容器的第二电容器，每个具有第二单位电容，其中所述第一单位电容器和所述第二单位电容器具有相等数目的单位电容器。 第一单元电容器和第二单元电容器以具有行和列的阵列排列并且以每行和每列置于交替图案中。 第一和第二单元电容器的总数大于2。

    Capacitor pairs with improved mismatch performance
    5.
    发明授权
    Capacitor pairs with improved mismatch performance 有权
    具有改善失配性能的电容对

    公开(公告)号：US07545022B2

    公开(公告)日：2009-06-09

    申请号：US11591644

    申请日：2006-11-01

    申请人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    发明人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.

    摘要翻译： 半导体器件包括：第一电容器，包括彼此互连的多个第一单位电容器，每个具有第一单位电容; 以及包括彼此互连的多个第二单位电容器的第二电容器，每个具有第二单位电容，其中所述第一单位电容器和所述第二单位电容器具有相等数目的单位电容器。 第一单元电容器和第二单元电容器以具有行和列的阵列排列并且以每行和每列置于交替图案中。 第一和第二单元电容器的总数大于2。

    Semiconductor device structure for reducing mismatch effects
    7.
    发明授权
    Semiconductor device structure for reducing mismatch effects 有权
    用于减少失配效应的半导体器件结构

    公开(公告)号：US08330251B2

    公开(公告)日：2012-12-11

    申请号：US11474762

    申请日：2006-06-26

    申请人： Chung-Long Chang ,  Chia-Yi Chen ,  Chih-Ping Chao

    发明人： Chung-Long Chang ,  Chia-Yi Chen ,  Chih-Ping Chao

    IPC分类号： H01L21/02

    CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip includes a first electronic device, a second electronic device, and a common electrode feature. The first electronic device includes a first feature. The first electronic device has a first footprint area in a given layer. The second electronic device includes a second feature. The second electronic device has a second footprint area in the given layer. The first and second electronic devices are electrically matched. The common electrode feature is common to the first and second electronic devices. The common electrode is at least partially located in the given layer. More than a majority of the first footprint area overlaps with the second footprint area. A first spacing between the first feature and the common electrode feature is about the same as a second spacing between the second feature and the common electrode feature.

    摘要翻译： 集成电路芯片包括第一电子器件，第二电子器件和公共电极特征。 第一电子设备包括第一特征。 第一电子设备在给定层中具有第一覆盖区域。 第二电子设备包括第二特征。 第二电子设备在给定层中具有第二覆盖区域。 第一和第二电子器件电气匹配。 公共电极特征对于第一和第二电子器件是共同的。 公共电极至少部分地位于给定层中。 第一个占地面积的绝大多数与第二个足迹区域重叠。 第一特征和公共电极特征之间的第一间隔与第二特征和公共电极特征之间的第二间隔大致相同。

    Capacitor pairs with improved mismatch performance
    8.
    发明授权
    Capacitor pairs with improved mismatch performance 有权
    具有改善失配性能的电容对

    公开(公告)号：US07923817B2

    公开(公告)日：2011-04-12

    申请号：US12463949

    申请日：2009-05-11

    申请人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    发明人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.

    摘要翻译： 半导体器件包括：第一电容器，包括彼此互连的多个第一单位电容器，每个具有第一单位电容; 以及包括彼此互连的多个第二单位电容器的第二电容器，每个具有第二单位电容，其中所述第一单位电容器和所述第二单位电容器具有相等数目的单位电容器。 第一单元电容器和第二单元电容器以具有行和列的阵列排列并且以每行和每列置于交替图案中。 第一和第二单元电容器的总数大于2。

    Semiconductor device structure for reducing mismatch effects
    10.
    发明申请
    Semiconductor device structure for reducing mismatch effects 有权
    用于减少失配效应的半导体器件结构

    公开(公告)号：US20070296013A1

    公开(公告)日：2007-12-27

    申请号：US11474762

    申请日：2006-06-26

    申请人： Chung-Long Chang ,  Chia-Yi Chen ,  Chih-Ping Chao

    发明人： Chung-Long Chang ,  Chia-Yi Chen ,  Chih-Ping Chao

    IPC分类号： H01L29/94

    CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip includes a first electronic device, a second electronic device, and a common electrode feature. The first electronic device includes a first feature. The first electronic device has a first footprint area in a given layer. The second electronic device includes a second feature. The second electronic device has a second footprint area in the given layer. The first and second electronic devices are electrically matched. The common electrode feature is common to the first and second electronic devices. The common electrode is at least partially located in the given layer. More than a majority of the first footprint area overlaps with the second footprint area. A first spacing between the first feature and the common electrode feature is about the same as a second spacing between the second feature and the common electrode feature.

    摘要翻译： 集成电路芯片包括第一电子器件，第二电子器件和公共电极特征。 第一电子设备包括第一特征。 第一电子设备在给定层中具有第一覆盖区域。 第二电子设备包括第二特征。 第二电子设备在给定层中具有第二覆盖区域。 第一和第二电子器件电气匹配。 公共电极特征对于第一和第二电子器件是共同的。 公共电极至少部分地位于给定层中。 第一个足迹区域的绝大多数与第二个足迹区域重叠。 第一特征和公共电极特征之间的第一间隔与第二特征和公共电极特征之间的第二间隔大致相同。