摘要:
A microprocessor system contains a read-only memory (ROM) for storing programs or firmware. Retrieval and execution of program code is controlled by a microprocessor address bus. Erroneous data in the ROM can be corrected by address comparison and translation. Trap, region, and patch tables are provided to store addresses, regions, and translated addresses. An address issued by the microprocessor is stored in the trap and region tables can be translated for selecting another programmable device, such as a SRAM or DRAM, other than the original ROM. Thus, erroneous code in the ROM can be corrected, inserted, or replaced.
摘要:
A microprocessor system contains a read-only memory (ROM) for storing programs or firmware. Retrieval and execution of program code is controlled by a microprocessor address bus. Erroneous data in the ROM can be corrected by address comparison and translation. Trap, region, and patch tables are provided to store addresses, regions, and translated addresses. An address issued by the microprocessor is stored in the trap and region tables can be translated for selecting another programmable device, such as a SRAM or DRAM, other than the original ROM. Thus, erroneous code in the ROM can be corrected, inserted, or replaced.
摘要:
According to the claimed invention, the controller is a chip with a memory connected to the program counter of a microcomputer apparatus. The chip is capable of comparing the value of the program counter against the value stored inside its own memory and issuing an indirect branch instruction with an index upon a match. The indirect branch instruction is capable of searching a table for an entry corresponding to the index and replacing the value of the program counter with the value of the entry in the table.
摘要:
According to the claimed invention, a microcomputer apparatus is disclosed. The microcomputer apparatus comprises a processing unit for executing instructions and a loop counter coupled to the processing unit for receiving and storing a loop count value according to a loop instruction executed by the processing unit wherein the processing unit decrements the loop count value stored in the loop counter each time an instruction is looped, and when the processing unit encounters a loop instruction, the processing unit will loop the instruction previous to the loop instruction a number of times as defined by the loop count value.