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公开(公告)号：US20090015235A1
公开(公告)日：2009-01-15
申请号：US11775115
申请日：2007-07-09
IPC分类号： G01R31/28
CPC分类号： G01R31/318505
摘要： A method for testing a system module assembled by integrated circuits during mass production. The integrated circuits and the assembled system modules are manufactured by the same manufacturer. The method includes the steps of apply a plurality of system level tests to the system module to determine the performance of the system module. Next, verify the performance of the integrated circuits based on the results of the system level tests. Finally, perform integrated circuit level tests, wherein the integrated circuit level tests include test items unverifiable by the system level tests. The present invention also includes a testing apparatus for testing a system module.
摘要翻译： 一种用于在批量生产期间测试由集成电路组装的系统模块的方法。 集成电路和组装的系统模块由相同的制造商制造。 该方法包括以下步骤：将多个系统级测试应用于系统模块以确定系统模块的性能。 接下来，根据系统级测试的结果，验证集成电路的性能。 最后，执行集成电路级测试，其中集成电路级测试包括通过系统级测试无法验证的测试项目。 本发明还包括用于测试系统模块的测试装置。
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公开(公告)号：US20080213991A1
公开(公告)日：2008-09-04
申请号：US11713038
申请日：2007-03-02
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , G01R1/0416 , G01R3/00 , H01L24/13 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/11452 , H01L2224/1146 , H01L2224/11622 , H01L2224/11831 , H01L2224/13016 , H01L2224/13124 , H01L2224/13147 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/14 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： The present invention is a method of forming plugs for engaging with a socket on a substrate having pads thereon. The method including the steps of forming an insulation layer on the substrate, patterning the insulation layer to form openings for exposing the pads by a wet etching, respectively, forming conductive plugs in the openings to electrically connect with the pads, and partially removing the insulation layer.
摘要翻译： 本发明是一种形成插头的方法，该插头用于与其上具有衬垫的衬底上的插座接合。 该方法包括以下步骤：在衬底上形成绝缘层，图案化绝缘层以形成用于通过湿蚀刻暴露焊盘的开口，在开口中形成导电插塞以与焊盘电连接，并部分地去除绝缘体 层。
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