公开(公告)号：US20080213991A1

公开(公告)日：2008-09-04

申请号：US11713038

申请日：2007-03-02

申请人： Wen-Jiunn Tsay ,  Bao-Tai Hwang ,  David Yow-Chern Chang ,  Ling-Haur Huang

发明人： Wen-Jiunn Tsay ,  Bao-Tai Hwang ,  David Yow-Chern Chang ,  Ling-Haur Huang

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  G01R1/0416 ,  G01R3/00 ,  H01L24/13 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11622 ,  H01L2224/11831 ,  H01L2224/13016 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The present invention is a method of forming plugs for engaging with a socket on a substrate having pads thereon. The method including the steps of forming an insulation layer on the substrate, patterning the insulation layer to form openings for exposing the pads by a wet etching, respectively, forming conductive plugs in the openings to electrically connect with the pads, and partially removing the insulation layer.

摘要翻译： 本发明是一种形成插头的方法，该插头用于与其上具有衬垫的衬底上的插座接合。 该方法包括以下步骤：在衬底上形成绝缘层，图案化绝缘层以形成用于通过湿蚀刻暴露焊盘的开口，在开口中形成导电插塞以与焊盘电连接，并部分地去除绝缘体 层。

公开(公告)号：US20090015235A1

公开(公告)日：2009-01-15

申请号：US11775115

申请日：2007-07-09

申请人： Wen-Jiunn Tsay ,  David Yow-Chern Chang ,  Bao-Tai Hwang ,  Ling-Haur Huang

发明人： Wen-Jiunn Tsay ,  David Yow-Chern Chang ,  Bao-Tai Hwang ,  Ling-Haur Huang

IPC分类号： G01R31/28

CPC分类号： G01R31/318505

摘要： A method for testing a system module assembled by integrated circuits during mass production. The integrated circuits and the assembled system modules are manufactured by the same manufacturer. The method includes the steps of apply a plurality of system level tests to the system module to determine the performance of the system module. Next, verify the performance of the integrated circuits based on the results of the system level tests. Finally, perform integrated circuit level tests, wherein the integrated circuit level tests include test items unverifiable by the system level tests. The present invention also includes a testing apparatus for testing a system module.

摘要翻译： 一种用于在批量生产期间测试由集成电路组装的系统模块的方法。 集成电路和组装的系统模块由相同的制造商制造。 该方法包括以下步骤：将多个系统级测试应用于系统模块以确定系统模块的性能。 接下来，根据系统级测试的结果，验证集成电路的性能。 最后，执行集成电路级测试，其中集成电路级测试包括通过系统级测试无法验证的测试项目。 本发明还包括用于测试系统模块的测试装置。

公开(公告)号：US4630356A

公开(公告)日：1986-12-23

申请号：US777800

申请日：1985-09-19

申请人： Rosemary Christie ,  Bao-Tai Hwang ,  San-Mei Ku ,  Janet M. Sickler

发明人： Rosemary Christie ,  Bao-Tai Hwang ,  San-Mei Ku ,  Janet M. Sickler

IPC分类号： H01L21/76 ,  H01L21/306 ,  H01L21/308 ,  H01L21/316 ,  H01L21/762 ,  H01L21/467 ,  H01L21/94

CPC分类号： H01L21/7621 ,  H01L21/3081

摘要： Disclosed is a method of forming in a monocrystalline silicon body an optimum recessed oxide isolation structure with reduced steepness of the bird's neck. Starting from a monocrystalline silicon body, there is formed thereon a layered structure of first silicon dioxide, polycrystalline silicon, second silicon dioxide and silicon nitride, in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form the oxide isolation pattern within the silicon body. The exposed areas of the silicon body are anisotropically reactive ion etched to an initial portion of the desired depth obtaining the corresponding portion of the trench having substantially vertical walls. Then by chemical etching the trench is extended to a final portion of the desired depth obtaining inwardly sloped walls in the final portion. The body is then thermally oxidized until the desired oxide isolation penetrates to the desired depth within the silicon body.

摘要翻译： 公开了一种在单晶硅体中形成具有降低的脖子陡度的最佳凹陷氧化物隔离结构的方法。 从单晶硅体开始，依次形成第一二氧化硅，多晶硅，第二二氧化硅和氮化硅的分层结构。 这些层被图案化以在期望在硅体内形成氧化物隔离图案的区域的结构中形成开口。 硅体的暴露区域是各向异性反应离子蚀刻到期望深度的初始部分，获得具有基本垂直壁的沟槽的相应部分。 然后通过化学蚀刻将沟槽延伸到所需深度的最后部分，从而获得最终部分中的向内倾斜的壁。 然后将身体热氧化直到所需的氧化物隔离渗入硅体内所需的深度。

公开(公告)号：US4681657A

公开(公告)日：1987-07-21

申请号：US793402

申请日：1985-10-31

申请人： Bao-Tai Hwang ,  Wendy A. Orr-Arienzo ,  Reinhard Glang

发明人： Bao-Tai Hwang ,  Wendy A. Orr-Arienzo ,  Reinhard Glang

IPC分类号： H01L21/306 ,  H01L21/308 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L21/30604 ,  H01L21/3081 ,  H01L21/3085

摘要： The present invention provides an improved etchant composition and method for the resistivity specific etching of doped silicon films which overlie intrinsic or lightly doped crystal regions. The composition of the etchant is 0.2-6 mole % hydrofluoric acid, 14-28 mole % nitric acid, and 66-86 mole % acetic acid/water. The etchant leaves no silicon residue and provides for controlled etching with an etch stop at the lightly doped or intrinsic region.

摘要翻译： 本发明提供了一种改进的蚀刻剂组成和方法，用于覆盖本征或轻掺杂晶体区域的掺杂硅膜的电阻率特异性蚀刻。 蚀刻剂的组成为0.2-6摩尔％氢氟酸，14-28摩尔％硝酸和66-86摩尔％乙酸/水。 蚀刻剂不留下硅残留物，并且在轻掺杂或固有区域提供用蚀刻停止层的受控蚀刻。