公开(公告)号：US07250332B2

公开(公告)日：2007-07-31

申请号：US10711038

申请日：2004-08-19

申请人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

发明人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6659

摘要： The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

摘要翻译： 本发明公开了一种半导体器件的制造方法。 提供基板。 具有侧壁的至少一个第一和第二栅极结构被包括在基板的表面上。 执行第一离子注入工艺以在基板中的第一栅极结构的每个侧壁旁边形成第一导电类型的浅结掺杂区域，随后在第一栅极结构的每个侧壁上形成偏置间隔物 和第二门结构。 执行第二离子注入工艺以在第二栅极结构的每个侧壁上的偏移间隔物旁边的衬底中形成第二导电类型的浅结掺杂区域。

公开(公告)号：US20060040448A1

公开(公告)日：2006-02-23

申请号：US10711038

申请日：2004-08-19

申请人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

发明人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

IPC分类号： H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6659

摘要： The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

摘要翻译： 本发明公开了一种半导体器件的制造方法。 提供基板。 具有侧壁的至少一个第一和第二栅极结构被包括在基板的表面上。 执行第一离子注入工艺以在基板中的第一栅极结构的每个侧壁旁边形成第一导电类型的浅结掺杂区域，随后在第一栅极结构的每个侧壁上形成偏置间隔物 和第二门结构。 执行第二离子注入工艺以在第二栅极结构的每个侧壁上的偏移间隔物旁边的衬底中形成第二导电类型的浅结掺杂区域。

公开(公告)号：US06372390B1

公开(公告)日：2002-04-16

申请号：US09584698

申请日：2000-06-01

申请人： En-Chuan Liu ,  Chiao-Lin Peng ,  Tai-Yuan Lee

发明人： En-Chuan Liu ,  Chiao-Lin Peng ,  Tai-Yuan Lee

IPC分类号： G03F900

CPC分类号： G03F1/40 ,  G03F1/50

摘要： The invention provides a photo mask with an electric discharge (ESD) protective function. The photo mask has a transparent substrate comprising quartz or glass, a patterned shielding layer located in the predetermined area of the surface of the transparent substrate, and an ESD protective layer positioned on the surface of the transparent substrate and surrounding the shielding layer. The ESD protective layer comprises a plurality of discharging peaks. The peaks aid in a neutralizing discharge reaction, which discharges harmful static electricity into the air.

摘要翻译： 本发明提供具有放电（ESD）保护功能的光掩膜。 光掩模具有包括石英或玻璃的透明基板，位于透明基板的表面的预定区域中的图案化屏蔽层以及位于透明基板的表面上且围绕屏蔽层的ESD保护层。 ESD保护层包括多个放电峰。 峰值有助于中和放电反应，将有害静电放入空气中。