公开(公告)号：US20060040448A1

公开(公告)日：2006-02-23

申请号：US10711038

申请日：2004-08-19

申请人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

发明人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

IPC分类号： H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6659

摘要： The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

摘要翻译： 本发明公开了一种半导体器件的制造方法。 提供基板。 具有侧壁的至少一个第一和第二栅极结构被包括在基板的表面上。 执行第一离子注入工艺以在基板中的第一栅极结构的每个侧壁旁边形成第一导电类型的浅结掺杂区域，随后在第一栅极结构的每个侧壁上形成偏置间隔物 和第二门结构。 执行第二离子注入工艺以在第二栅极结构的每个侧壁上的偏移间隔物旁边的衬底中形成第二导电类型的浅结掺杂区域。

公开(公告)号：US07250332B2

公开(公告)日：2007-07-31

申请号：US10711038

申请日：2004-08-19

申请人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

发明人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6659

摘要： The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

摘要翻译： 本发明公开了一种半导体器件的制造方法。 提供基板。 具有侧壁的至少一个第一和第二栅极结构被包括在基板的表面上。 执行第一离子注入工艺以在基板中的第一栅极结构的每个侧壁旁边形成第一导电类型的浅结掺杂区域，随后在第一栅极结构的每个侧壁上形成偏置间隔物 和第二门结构。 执行第二离子注入工艺以在第二栅极结构的每个侧壁上的偏移间隔物旁边的衬底中形成第二导电类型的浅结掺杂区域。

公开(公告)号：US08084769B2

公开(公告)日：2011-12-27

申请号：US11675635

申请日：2007-02-16

申请人： Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da-Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

发明人： Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da-Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： H01L22/34

摘要： A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.

摘要翻译： 测试键设计模式包括至少一个导电触点，垂直并电连接到导电触点的至少一个第一宽度的导线和分别直接连接到导线的每一侧的至少一对源极和漏极。 一对源极和漏极以及直接连接到源极和漏极的第一长度的导电线的一部分形成电子器件。 测试键设计模式在测量电容时具有较小误差和更好的栅极氧化物厚度提取的优势。

公开(公告)号：US20080197351A1

公开(公告)日：2008-08-21

申请号：US11675635

申请日：2007-02-16

申请人： Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da- Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

发明人： Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da- Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

IPC分类号： H01L23/58

CPC分类号： H01L22/34

摘要： A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.

摘要翻译： 测试键设计模式包括至少一个导电触点，垂直并电连接到导电触点的至少一个第一宽度的导线和分别直接连接到导线的每一侧的至少一对源极和漏极。 一对源极和漏极以及直接连接到源极和漏极的第一长度的导电线的一部分形成电子器件。 测试键设计模式在测量电容时具有较小误差和更好的栅极氧化物厚度提取的优势。

公开(公告)号：US08796805B2

公开(公告)日：2014-08-05

申请号：US13604380

申请日：2012-09-05

申请人： Shyh-Fann Ting ,  Jiech-Fun Lu ,  Ming-I Wang ,  Yeur-Luen Tu ,  Ching-Chun Wang

发明人： Shyh-Fann Ting ,  Jiech-Fun Lu ,  Ming-I Wang ,  Yeur-Luen Tu ,  Ching-Chun Wang

IPC分类号： H01L31/00 ,  H01L21/00 ,  H01L27/146 ,  H01L21/768

CPC分类号： H01L27/1464 ,  H01L21/76838 ,  H01L27/14623 ,  H01L27/14687

摘要： A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.

摘要翻译： 一种方法包括形成从半导体衬底的背表面延伸到半导体衬底的前侧上的金属焊盘的开口，以及在半导体衬底中形成包括与有源图像传感器重叠的第一部分的第一导电层，第二部分 半导体衬底中重叠的黑色参考图像传感器，以及开口中的与金属垫接触的第三部分。 在第一导电层上形成第二导电层并与第一导电层接触。 执行第一图案化步骤以去除第二导电层的第一和第二部分，其中第一导电层用作蚀刻停止层。 执行第二图案化步骤以去除第一导电层的第一部分的一部分。 在第二图案化步骤之后，第一导电层的第二和第三部分保留。

公开(公告)号：US20120199890A1

公开(公告)日：2012-08-09

申请号：US13450444

申请日：2012-04-18

申请人： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

发明人： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC分类号： H01L29/78

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

摘要： A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.

摘要翻译： 在本发明中提供一种晶体管结构。 晶体管结构包括：包括P型阱的衬底，设置在P型阱上的栅极，设置在栅极上的第一间隔物，设置在栅极两侧的衬底中的N型源极/漏极区域 覆盖N型源极/漏极区域的硅覆盖层，围绕第一间隔物的第二间隔物和第二间隔物，直接覆盖硅覆盖层的一部分并且覆盖硅覆盖层上的硅化物层。

公开(公告)号：US07928512B2

公开(公告)日：2011-04-19

申请号：US11776562

申请日：2007-07-12

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

IPC分类号： H01L27/12

CPC分类号： H01L21/823412 ,  H01L21/823468 ,  H01L29/7842

摘要： A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.

摘要翻译： 本文提供了一种半导体器件，其包括具有第一型MOS晶体管，形成在其上的输入/输出（I / O）第二型MOS晶体管和核心第二型MOS晶体管的衬底。 半导体器件还包括第一应力层和第二应力层。 第一应力层设置在第一型MOS晶体管上或第一型MOS晶体管和I / O第二型MOS晶体管上。 第二应力层设置在芯型二次型MOS晶体管上。

公开(公告)号：US20090137089A1

公开(公告)日：2009-05-28

申请号：US12366625

申请日：2009-02-05

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC分类号： H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 栅介质层形成在衬底的有源区上。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化物间隔物。 进行离子注入以形成源极/漏极区域。 在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。 去除氮化物间隔物。 与衬垫相邻的氮化物覆盖层被沉积。 氮化物盖层具有特定的应力状态。

公开(公告)号：US20080206942A1

公开(公告)日：2008-08-28

申请号：US11678627

申请日：2007-02-26

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

摘要翻译： 公开了制造应变硅晶体管的方法。 首先，提供半导体衬底，并且在半导体衬底上设置栅极结构和围绕栅极结构的间隔物。 然后在隔离物周围的半导体衬底中形成源极/漏极区域，并且执行第一快速热退火处理以激活源极/漏极区域内的掺杂剂。 执行蚀刻工艺以在栅极结构周围形成凹陷，并且执行选择性外延生长工艺以在凹部中形成外延层。 执行第二快速热退火处理以重新定义源/漏区域内的掺杂剂的分布并修复掺杂剂的损坏的键。

公开(公告)号：US07342284B2

公开(公告)日：2008-03-11

申请号：US11307660

申请日：2006-02-16

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC分类号： H01L29/94

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 栅介质层形成在衬底的有源区上。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化物间隔物。 进行离子注入以形成源极/漏极区域。 在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。 去除氮化物间隔物。 与衬垫相邻的氮化物覆盖层被沉积。 氮化物盖层具有特定的应力状态。