公开(公告)号：US08094493B2

公开(公告)日：2012-01-10

申请号：US11271300

申请日：2005-11-10

申请人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

发明人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

IPC分类号： G11C11/34 ,  G11C7/02

CPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/0475 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50004 ,  G11C2211/5634

摘要： A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding reference line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

摘要翻译： 公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。 存储装置还包括多个参考线和参考单元。 每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。 来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考 当前修剪）。

公开(公告)号：US20060104113A1

公开(公告)日：2006-05-18

申请号：US11271300

申请日：2005-11-10

申请人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

发明人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/0475 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50004 ,  G11C2211/5634

摘要： A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding referece line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

摘要翻译： 公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。 存储装置还包括多个参考线和参考单元。 每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。 来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考 当前修剪）。

公开(公告)号：US07295471B2

公开(公告)日：2007-11-13

申请号：US11273120

申请日：2005-11-14

申请人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

发明人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459

摘要： A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.

摘要翻译： 具有包括多个存储单元的虚拟阵列的存储器件的程序验证方法确定漏电流是否通过一个或多个相邻的存储器单元到编程的存储器单元。 如果确定泄漏电流通过一个或多个相邻存储器单元，则基于第一阈值状态来验证编程存储器单元。 如果泄漏电流未被确定通过一个或多个相邻存储器单元，则基于第二阈值状态来验证编程存储器单元。

公开(公告)号：US20060109710A1

公开(公告)日：2006-05-25

申请号：US11273120

申请日：2005-11-14

申请人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

发明人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/0475 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459

摘要： A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.

摘要翻译： 具有包括多个存储单元的虚拟阵列的存储器件的程序验证方法确定漏电流是否通过一个或多个相邻的存储器单元到编程的存储器单元。 如果确定泄漏电流通过一个或多个相邻存储器单元，则基于第一阈值状态来验证编程存储器单元。 如果泄漏电流未被确定通过一个或多个相邻存储器单元，则基于第二阈值状态来验证编程存储器单元。

公开(公告)号：US20060092709A1

公开(公告)日：2006-05-04

申请号：US11096878

申请日：2005-04-01

申请人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

发明人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

摘要： A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

公开(公告)号：US08174904B2

公开(公告)日：2012-05-08

申请号：US12898691

申请日：2010-10-05

申请人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

发明人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

摘要： An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.

摘要翻译： 本发明的一个实施例提供一种包括多个位线，多个存储单元和一个设备的存储器阵列。 多个存储单元中的每一个具有第一节点，第二节点和第三节点，其中第三节点耦合到多个位线之一。 该设备将多个位线耦合在一起以形成多个存储器单元之一的公共节点。

公开(公告)号：US07830723B2

公开(公告)日：2010-11-09

申请号：US12423013

申请日：2009-04-14

申请人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

发明人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

摘要： A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

摘要翻译： NROM存储器件包括存储器单元阵列和第一和第二位线。 第一和第二位线耦合到存储器单元的相对侧。 在擦除操作期间，存储器单元的一侧接收正电压，另一侧耦合到公共节点或有限电流源。 还公开了可以容易地基于存储器单元的阈值电压分布来筛选边际存储器单元的方法。

公开(公告)号：US07535771B2

公开(公告)日：2009-05-19

申请号：US11096878

申请日：2005-04-01

申请人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

发明人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

摘要： A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

摘要翻译： NROM存储器件包括存储器单元阵列和第一和第二位线。 第一和第二位线耦合到存储器单元的相对侧。 在擦除操作期间，存储器单元的一侧接收正电压，另一侧耦合到公共节点或有限电流源。 还公开了可以基于存储器单元的阈值电压分布容易地筛选边际存储器单元的方法。

公开(公告)号：US20110019473A1

公开(公告)日：2011-01-27

申请号：US12898691

申请日：2010-10-05

申请人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

发明人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

摘要： An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.

摘要翻译： 本发明的一个实施例提供一种包括多个位线，多个存储单元和一个设备的存储器阵列。 多个存储单元中的每一个具有第一节点，第二节点和第三节点，其中第三节点耦合到多个位线之一。 该设备将多个位线耦合在一起以形成多个存储器单元之一的公共节点。

公开(公告)号：US20090225605A1

公开(公告)日：2009-09-10

申请号：US12423013

申请日：2009-04-14

申请人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

发明人： Wen-Yi Hsieh ,  Ching-Chung Lin ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC分类号： G11C16/04 ,  G11C5/14

CPC分类号： G11C16/0475 ,  G11C16/04 ,  G11C16/3445 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52

摘要： A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

摘要翻译： NROM存储器件包括存储器单元阵列和第一和第二位线。 第一和第二位线耦合到存储器单元的相对侧。 在擦除操作期间，存储器单元的一侧接收正电压，另一侧耦合到公共节点或有限电流源。 还公开了可以容易地基于存储器单元的阈值电压分布来筛选边际存储器单元的方法。