公开(公告)号：US10896123B2

公开(公告)日：2021-01-19

申请号：US16218800

申请日：2018-12-13

Applicant: Western Digital Technologies, Inc.

Inventor： Nian Niles Yang ,  Sahil Sharma ,  Philip Reusswig ,  Rohit Sehgal

IPC: G06F12/02 ,  G11C16/34 ,  G11C29/42 ,  G06F11/10 ,  G11C29/52 ,  H04L1/20

Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

公开(公告)号：US10559366B2

公开(公告)日：2020-02-11

申请号：US15941747

申请日：2018-03-30

Applicant: Western Digital Technologies, Inc.

Inventor： Zhenlei Shen ,  Pitamber Shukla ,  Philip Reusswig ,  Niles N. Yang ,  Anubhav Khandelwal

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C29/50 ,  G11C16/26

Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.

公开(公告)号：US10255000B2

公开(公告)日：2019-04-09

申请号：US15408943

申请日：2017-01-18

Applicant: Western Digital Technologies, Inc.

Inventor： Sahil Sharma ,  Philip Reusswig ,  Nian Niles Yang ,  Rohit Sehgal ,  Gautham Reddy

IPC: G06F3/06 ,  G11C16/28 ,  G11C16/10 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: A memory device and associated techniques avoid reading memory cells immediately after programming when uncorrectable errors may be present. In one aspect, data is copied from one block to another block and a timer is started after the copying is completed. If a read command is received before the timer has expired, the read operation proceeds by reading the one block. If the read command is received after the timer has expired, the read operation proceeds by reading the another block. This approach is particular suitable when data is copied from single-level cell (SLC) blocks to multi-level cell (MLC) blocks in a folding operation. The duration of the timer can be increased at lower temperatures.

公开(公告)号：US10573397B1

公开(公告)日：2020-02-25

申请号：US16209519

申请日：2018-12-04

Applicant: Western Digital Technologies, Inc.

Inventor： Rohit Sehgal ,  Sahil Sharma ,  Philip Reusswig ,  Nian Niles Yang

IPC: G11C16/34 ,  G11C11/56 ,  G06F11/07

Abstract: On a non-volatile memory circuit, peripheral circuitry generates programming voltages based on parameter values. If parameter values are incorrectly translated into programming voltages, data may be over-programmed, resulting in high bit error rates (BERs). The memory system can monitor the error rates using memory cell voltage distributions for different portions of the memory and look for signatures of such incorrect implementation. For example, by monitoring the BER along word lines that are most prone to error due to incorrectly implemented programming parameters, the memory system can determine if the programming parameters for the corresponding portion of a memory device indicate such anomalous behavior. If such a signature is found, the memory system checks to see whether the programming parameters should be adjusted, such as by comparing the programming parameters used on one die to programming parameters used on another die of the memory system, and adjust the programming parameters accordingly.

公开(公告)号：US10324859B2

公开(公告)日：2019-06-18

申请号：US15633388

申请日：2017-06-26

Applicant: Western Digital Technologies, Inc.

Inventor： Daniel Joseph Linnen ,  Ashish Ghai ,  Dongxiang Liao ,  Srikar Peesari ,  Avinash Rajagiri ,  Philip Reusswig ,  Bin Wu

IPC: G06F12/10 ,  G06F12/1036 ,  G06F3/06 ,  G06F11/10 ,  G06F11/14

Abstract: Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

公开(公告)号：US20180373644A1

公开(公告)日：2018-12-27

申请号：US15633388

申请日：2017-06-26

Applicant: Western Digital Technologies, Inc.

Inventor： Daniel Joseph Linnen ,  Ashish Ghai ,  Dongxiang Liao ,  Srikar Peesari ,  Avinash Rajagiri ,  Philip Reusswig ,  Bin Wu

IPC: G06F12/1036 ,  G06F3/06 ,  G06F11/10 ,  G06F11/14 ,  G06F12/10

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

公开(公告)号：US20180203642A1

公开(公告)日：2018-07-19

申请号：US15408943

申请日：2017-01-18

Applicant: Western Digital Technologies, Inc.

Inventor： Sahil Sharma ,  Philip Reusswig ,  Nian Niles Yang ,  Rohit Sehgal ,  Gautham Reddy

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/0647 ,  G06F3/0679 ,  G06F3/0688 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/3459

Abstract: A memory device and associated techniques avoid reading memory cells immediately after programming when uncorrectable errors may be present. In one aspect, data is copied from one block to another block and a timer is started after the copying is completed. If a read command is received before the timer has expired, the read operation proceeds by reading the one block. If the read command is received after the timer has expired, the read operation proceeds by reading the another block. This approach is particular suitable when data is copied from single-level cell (SLC) blocks to multi-level cell (MLC) blocks in a folding operation. The duration of the timer can be increased at lower temperatures.