-
1.发明授权
公开(公告)号：US5982694A
公开(公告)日：1999-11-09
申请号：US747120
申请日：1996-11-08
申请人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译： 同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。 同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。 同步随机存取存储器件可以制造为动态存储器件或静态存储器件。
-
2.发明授权Data processing system arranged for operating synchronously with a high speed memory 失效数据处理系统被布置成与高速存储器同步操作
公开(公告)号：US5912854A
公开(公告)日：1999-06-15
申请号：US905751
申请日：1997-08-04
申请人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译： 同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。 同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。 同步随机存取存储器件可以制造为动态存储器件或静态存储器件。
-
3.发明授权Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock 失效具有布置成与微处理器同步操作的延迟的随机存取存储器以及包括数据处理器，同步DRAM，外围设备和系统时钟的系统
公开(公告)号：US5808958A
公开(公告)日：1998-09-15
申请号：US477735
申请日：1995-06-07
申请人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译： 同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。 同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。 同步随机存取存储器件可以制造为动态存储器件或静态存储器件。
-
4.发明授权
公开(公告)号：US6088280A
公开(公告)日：2000-07-11
申请号：US413928
申请日：1999-10-07
申请人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译： 同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。 同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。 同步随机存取存储器件可以制造为动态存储器件或静态存储器件。
-
5.发明授权Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock 失效布置成与微处理器同步操作的随机存取存储器和包括数据处理器，同步DRAM，外围设备和系统时钟的系统
公开(公告)号：US5587954A
公开(公告)日：1996-12-24
申请号：US327540
申请日：1994-10-21
申请人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译： 同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。 同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。 同步随机存取存储器件可以制造为动态存储器件或静态存储器件。
-
6.发明授权System including a data processor, a synchronous dram, a peripheral device, and a system clock 失效系统包括数据处理器，同步电平，外围设备和系统时钟
公开(公告)号：US5390149A
公开(公告)日：1995-02-14
申请号：US184749
申请日：1994-01-21
申请人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译： 同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。 同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。 同步随机存取存储器件可以制造为动态存储器件或静态存储器件。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.05 秒)
