公开(公告)号：US5902044A

公开(公告)日：1999-05-11

申请号：US883911

申请日：1997-06-27

申请人： Wilbur Pricer ,  Kenneth Joseph Goodnow ,  Michel S. Michail ,  Janak Ghanshyambhai Patel ,  Sebastian T. Ventrone

发明人： Wilbur Pricer ,  Kenneth Joseph Goodnow ,  Michel S. Michail ,  Janak Ghanshyambhai Patel ,  Sebastian T. Ventrone

IPC分类号： G01K3/14 ,  G01K7/00

CPC分类号： G01K3/14

摘要： A matrix of thermal sensors is provided for accurately evaluating the thermal characteristics of an integrated circuit. The integrated circuit is evenly divided into a plurality of sectors in which a thermal comparison to a known thermal mass will be performed. Each sector includes at least one dual cell comprising a local thermal sensor for providing an output corresponding to a local temperature of the integrated circuit in that sector, and a background thermal sensor. The outputs of selective ones of the background thermal sensors are combined to provide a signal corresponding to a background temperature of the integrated circuit. A decoder/enabler arrangement is used to selectively gate the output of a specific local thermal sensor in a sector to a difference circuit where it is compared to the collective output of selected ones of the background sensors to generate a thermal measurement of the sector under test.

摘要翻译： 提供了一种热传感器矩阵，用于精确评估集成电路的热特性。 集成电路被均匀地分成多个扇区，其中将对已知的热质量进行热比较。 每个扇区包括至少一个双电池，其包括本地热传感器，用于提供对应于该扇区中的集成电路的局部温度的输出和背景热传感器。 背景热传感器中的选择性传感器的输出被组合以提供对应于集成电路的背景温度的信号。 解码器/使能器布置用于选择性地将扇区中的特定局部热传感器的输出门控到差分电路，其中与所选择的背景传感器的集合输出进行比较以产生被测扇区的热测量 。

公开(公告)号：US5929646A

公开(公告)日：1999-07-27

申请号：US766234

申请日：1996-12-13

申请人： Janak Ghanshyambhai Patel ,  Dana John Thygesen

发明人： Janak Ghanshyambhai Patel ,  Dana John Thygesen

IPC分类号： G01R1/073 ,  G01R1/07

CPC分类号： G01R1/07378

摘要： The preferred embodiment of the present invention provides an apparatus and method to facilitate the testing of semiconductor devices packaged in surface mount modules (such as ball grid array modules and cylinder grid array modules) while the module is connected to a system board. The preferred embodiment provides an interposer mechanism that includes a top array of interposer landing pads and a bottom array of interposer landing pads. The bottom array of interposer landing pads are connected to the top array of interposer landing pads. The preferred embodiment also provides a module test card mechanism. The module test card mechanism includes a plurality of landing pads arranged to receive the surface mount module. The plurality of landing pads are connected to a plurality of test pins, and a plurality of landing pads underneath the module test card mechanism. The surface mount module can be coupled the system board through the module test card mechanism and the interposer mechanism with the plurality of test pins providing access to the semiconductor device for testing.

摘要翻译： 本发明的优选实施例提供了一种在模块连接到系统板时便于测试封装在表面贴装模块（例如球栅阵列模块和气缸网格阵列模块）中的半导体器件的装置和方法。 优选实施例提供一种插入器机构，其包括插入件着陆焊盘的顶部阵列和插入件着陆焊盘的底部阵列。 内插器着陆焊盘的底部阵列连接到中间层着陆焊盘的顶部阵列。 优选实施例还提供了一种模块测试卡机制。 模块测试卡机构包括布置成接收表面安装模块的多个着陆焊盘。 多个着陆焊盘连接到多个测试引脚和在模块测试卡机构下方的多个着陆焊盘。 表面安装模块可以通过模块测试卡机构与系统板耦合，并且插入器机构与多个测试引脚相连接，提供对半导体器件的访问以进行测试。