公开(公告)号：US20130009685A1

公开(公告)日：2013-01-10

申请号：US13613342

申请日：2012-09-13

申请人： Seung Jun BAE ,  Kwang Il PARK ,  Young-Sik KIM ,  Sang Hyup KWAK

发明人： Seung Jun BAE ,  Kwang Il PARK ,  Young-Sik KIM ,  Sang Hyup KWAK

IPC分类号： H03L7/00

CPC分类号： H03K5/1565 ,  H03K2005/0013

摘要： A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.

摘要翻译： 用于集成电路装置的数据I / O接口包括接收电源电压的噪声检测器，检测电源电压噪声分量，以及响应于检测到的电源电压噪声分量提供时钟延迟控制信号。 数据I / O接口还包括响应于时钟延迟控制信号提供延迟时钟信号的时钟延迟电路和由电源电压供电并且与延迟的时钟信号同步地提供输出数据的数据传输电路。

公开(公告)号：US20110133748A1

公开(公告)日：2011-06-09

申请号：US12959302

申请日：2010-12-02

申请人： Yusuke HAYASE ,  Toshiyuki OKAYASU

发明人： Yusuke HAYASE ,  Toshiyuki OKAYASU

IPC分类号： H03H11/26 ,  H03K5/01 ,  G01R31/02

CPC分类号： G01R31/31922 ,  G01R31/3016 ,  H03K5/13 ,  H03K5/135 ,  H03K2005/0013

摘要： Provided is a signal output circuit that outputs a signal, comprising an output circuit that changes a characteristic of a signal output therefrom according to a change in power supply voltage supplied thereto and a control signal supplied thereto; and a control section that changes the control signal to compensate for a change in the characteristic due to a change in the power supply voltage.

摘要翻译： 提供一种输出信号的信号输出电路，包括根据供给的电源电压的变化和提供给其的电源电压的变化而改变从其输出的信号的特性的输出电路; 以及控制部分，其改变控制信号以补偿由于电源电压的变化引起的特性的变化。

公开(公告)号：US07936225B2

公开(公告)日：2011-05-03

申请号：US12333665

申请日：2008-12-12

申请人： Takeshi Osada

发明人： Takeshi Osada

IPC分类号： H03K3/03

CPC分类号： H03L7/0995 ,  H03K5/133 ,  H03K2005/00039 ,  H03K2005/0013 ,  H03L7/18

摘要： A VCO circuit includes: a control portion to which a first voltage is inputted and from which a second voltage corresponding to the first voltage is outputted; a current source portion to which the second voltage is inputted and from which a current corresponding to the second voltage is outputted; and an oscillator circuit to which the current is inputted and from which a signal with a frequency in accordance with the current is outputted. The control portion includes an adjusting circuit which changes the second voltage in conjunction with fluctuation of a power supply voltage. Accordingly, fluctuation of the frequency Fo of an output signal of the VCO circuit can be suppressed even when the power supply voltage of the VCO circuit fluctuates.

摘要翻译： VCO电路包括：输入第一电压并从其输出与第一电压对应的第二电压的控制部分; 输入第二电压的电流源部，并输出与第二电压对应的电流; 以及输入电流的振荡器电路，并且从该振荡器电路输出具有与电流相关的频率的信号。 控制部分包括调整电路，其随着电源电压的波动而改变第二电压。 因此，即使当VCO电路的电源电压波动时也可以抑制VCO电路的输出信号的频率Fo的波动。

公开(公告)号：US07882408B1

公开(公告)日：2011-02-01

申请号：US11546743

申请日：2006-10-11

申请人： Kok Heng Choe ,  Edwin Yew Fatt Kok ,  Kar Keng Chua

发明人： Kok Heng Choe ,  Edwin Yew Fatt Kok ,  Kar Keng Chua

IPC分类号： G11C29/00 ,  G11B5/00 ,  G06F11/00

CPC分类号： H03K5/13 ,  H03K19/173 ,  H03K2005/0013 ,  H03K2005/00143

摘要： Memory performance in programmable logic is significantly increased by adjusting a timing of control signals sent to a memory to compensate for variations in process, voltage, or temperature. A calibration circuit can adjust the control signal timing, dynamically and automatically, to provide accurate and high performance memory operations. For example, timing settings for the control signals can be determined such that data written/read from the memory are accurate. The timing setting can also be changed to provide faster memory operations while still providing accuracy. A feedback system using a control block and a dummy mimicking concept are also provided.

摘要翻译： 通过调整发送到存储器的控制信号的时序来补偿过程，电压或温度的变化，可编程逻辑中的存储器性能显着增加。 校准电路可以动态和自动地调整控制信号时序，以提供精确和高性能的存储器操作。 例如，可以确定控制信号的定时设置，使得从存储器写入/读取的数据是准确的。 时序设置也可以改变，以提供更快的存储器操作，同时仍然提供准确性。 还提供了使用控制块和虚拟模拟概念的反馈系统。

公开(公告)号：US20100259310A1

公开(公告)日：2010-10-14

申请号：US12754794

申请日：2010-04-06

申请人： Seung Jun BAE ,  Kwang Il PARK ,  Young-Sik KIM ,  Sang Hyup KWAK

发明人： Seung Jun BAE ,  Kwang Il PARK ,  Young-Sik KIM ,  Sang Hyup KWAK

IPC分类号： H03H11/26

CPC分类号： H03K5/1565 ,  H03K2005/0013

摘要： A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.

摘要翻译： 用于集成电路装置的数据I / O接口包括接收电源电压的噪声检测器，检测电源电压噪声分量，以及响应于检测到的电源电压噪声分量提供时钟延迟控制信号。 数据I / O接口还包括响应于时钟延迟控制信号提供延迟时钟信号的时钟延迟电路和由电源电压供电并且与延迟的时钟信号同步地提供输出数据的数据传输电路。

公开(公告)号：US07733150B2

公开(公告)日：2010-06-08

申请号：US12192385

申请日：2008-08-15

申请人： Chiaki Takano

发明人： Chiaki Takano

IPC分类号： G06F1/04

CPC分类号： H03K5/13 ,  H03K5/1506 ,  H03K2005/00039 ,  H03K2005/0013

摘要： Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.

摘要翻译： 用于将时钟信号分配给数字电路的方法和装置提供：产生时钟信号; 并且延迟，提前或者使时钟信号不变以产生作为控制信号的函数的输出时钟信号，其中时钟信号和输出时钟信号之间的延迟或提前量（相位差）是时间的函数 变化到数字电路的电源电压的大小。

公开(公告)号：US07692459B2

公开(公告)日：2010-04-06

申请号：US11878411

申请日：2007-07-24

申请人： Chao-Cheng Lee

发明人： Chao-Cheng Lee

IPC分类号： H03H9/38 ,  H03M1/12

CPC分类号： H03K5/131 ,  H03K2005/00117 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143

摘要： A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.

摘要翻译： 一种用于调整信号的延迟时间的延迟调整器，所述调整器包括：第一电容单元和串联耦合到所述第一电容器的可变电容单元，其中根据第一控制信号调整所述可变电容单元的电容， 电容单元包括多个第二电容器和耦合到第二电容器的至少一个电容器的至少第一开关。

公开(公告)号：US20090185413A1

公开(公告)日：2009-07-23

申请号：US12136878

申请日：2008-06-11

申请人： Mi Hye KIM ,  Jae Jin LEE

发明人： Mi Hye KIM ,  Jae Jin LEE

IPC分类号： H03K5/12 ,  G11C11/34

CPC分类号： G11C5/147 ,  G11C5/143 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/00384 ,  H03K2005/0013 ,  H03K2005/00208

摘要： A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes an input potential detection unit outputting a detection signal in response to a level of an input signal, an input buffer buffering the input signal, and an output path control unit that receives the output signal of the input buffer and the detection signal of the input potential detection unit and outputs an output driving signal in response to the level of the detection signal.

摘要翻译： 半导体器件最小化输入缓冲器的输出信号偏斜的产生，从而稳定半导体器件的操作。 半导体集成电路包括输入电位检测单元，其响应于输入信号的电平，缓冲输入信号的输入缓冲器和接收输入缓冲器的输出信号和检测的输出路径控制单元输出检测信号 信号，并且响应于检测信号的电平而输出输出驱动信号。

公开(公告)号：US20090160562A1

公开(公告)日：2009-06-25

申请号：US12193042

申请日：2008-08-17

申请人： Hsien-Sheng Huang

发明人： Hsien-Sheng Huang

IPC分类号： H03L1/00 ,  H03B5/12 ,  H03K3/03

CPC分类号： H03K3/0315 ,  H03K3/011 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143 ,  H03K2005/00202 ,  H03L1/00

摘要： The present invention provides an oscillating device. The oscillating device includes: a voltage regulating module, a current generating module, and an oscillating module. The voltage regulating module is utilized for generating a control voltage at an output terminal, and the voltage regulating module includes: a first operational amplifier, a first switch element, and a first voltage dividing circuit. The oscillating module includes: a plurality of switch modules connected in series, a current mirror module, and a plurality of capacitor modules. In the oscillating device of the present invention, a frequency of an oscillating signal outputted by the oscillating module will not be affected by voltage offset of an operating voltage, environment temperature variations, or semiconductor process variations.

摘要翻译： 本发明提供一种摆动装置。 振荡装置包括：电压调节模块，电流产生模块和振荡模块。 电压调节模块用于在输出端产生控制电压，电压调节模块包括：第一运算放大器，第一开关元件和第一分压电路。 振荡模块包括：串联连接的多个开关模块，电流镜模块和多个电容器模块。 在本发明的振荡装置中，由振荡模块输出的振荡信号的频率不受工作电压，环境温度变化或半导体工艺变化的电压偏移的影响。

公开(公告)号：US20090146718A1

公开(公告)日：2009-06-11

申请号：US12203923

申请日：2008-09-04

申请人： Leaf Chen

发明人： Leaf Chen

IPC分类号： H03H11/26

CPC分类号： H03H11/26 ,  H03K5/13 ,  H03K2005/0013 ,  H03K2005/00163

摘要： A delay circuit is disclosed for providing highly stable delay time in digital signal processing. The delay circuit includes a preliminary charging/discharging circuit, a signal processing circuit and an output circuit. The preliminary charging/discharging circuit performs charging and discharging operations based on a logic input signal for generating a voltage signal. The signal processing circuit performs signal processing on the voltage signal for generating a first delay signal and a second delay signal. The output circuit performs logic signal processing on the first and second delay signals for generating a logic output signal lagging behind the logic input signal by a delay time. The delay time is independent of any supply voltage. That is, even though the supply voltage is unstable, the delay circuit is capable of generating a stable logic output signal by performing a signal delay process on a logic input signal regardless of the unstable supply voltage.

摘要翻译： 公开了一种用于在数字信号处理中提供高度稳定的延迟时间的延迟电路。 延迟电路包括预备充电/放电电路，信号处理电路和输出电路。 预充电/放电电路基于用于产生电压信号的逻辑输入信号进行充放电操作。 信号处理电路对电压信号执行信号处理，以产生第一延迟信号和第二延迟信号。 输出电路对第一和第二延迟信号执行逻辑信号处理，以产生滞后于逻辑输入信号延迟时间的逻辑输出信号。 延迟时间与任何电源电压无关。 也就是说，即使电源电压不稳定，延迟电路能够通过对逻辑输入信号执行信号延迟处理来产生稳定的逻辑输出信号，而不管电源电压不稳定。