公开(公告)号：US07315971B2

公开(公告)日：2008-01-01

申请号：US11243898

申请日：2005-10-04

申请人： William E. Grose ,  Lonnie L. Lambert ,  Jeanne Krayer Pitz ,  Toru Tanaka

发明人： William E. Grose ,  Lonnie L. Lambert ,  Jeanne Krayer Pitz ,  Toru Tanaka

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G11C16/04 ,  G11C29/48 ,  G11C2029/3202

摘要： A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. A selector input controls each of the plurality of selector devices, which is electrically coupled to a respective one of the memory cells, and is indirectly coupled to one of the plurality of latch devices. A load clock loads a pattern into the plurality of latch devices. A derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices with the assertion of the selector input. A system clock loads the derivative of the pattern into the plurality of latch devices.

摘要翻译： 一种用于测试包括数字和模拟部分的设备的方法和系统。 数字部分包括多个锁存装置，并且模拟部分包括多个存储单元和多个选择装置。 选择器输入控制多个选择器装置中的每一个，其被电耦合到相应的一个存储器单元，并且间接地耦合到多个锁存装置中的一个。 负载时钟将模式加载到多个锁存器件中。 模式的导数由多个选择器接收，并且通过选择器输入的断言返回到多个锁存装置。 系统时钟将模式的导数加载到多个锁存器件中。

公开(公告)号：US20070168776A1

公开(公告)日：2007-07-19

申请号：US11243898

申请日：2005-10-04

申请人： William Grose ,  Lonnie Lambert ,  Jeanne Krayer Pitz ,  Toru Tanaka

发明人： William Grose ,  Lonnie Lambert ,  Jeanne Krayer Pitz ,  Toru Tanaka

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G11C16/04 ,  G11C29/48 ,  G11C2029/3202

摘要： Systems, methods and circuits for implementing efficient device testing. As one example, a method is disclosed for testing a device that includes both a digital and analog portion. In some cases, the digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. Each of the plurality of selector devices is electrically coupled to a respective one of the memory cells, is at least indirectly coupled to one of the plurality of latch, devices, and is controlled by a selector input. In the method, a load clock is applied to the plurality of latch devices such that a pattern is loaded into the plurality of latch devices. The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices. A system clock is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.

摘要翻译： 用于实现高效设备测试的系统，方法和电路。 作为一个示例，公开了一种用于测试包括数字和模拟部分的设备的方法。 在一些情况下，数字部分包括多个锁存装置，并且模拟部分包括多个存储器单元和多个选择器装置。 多个选择器装置中的每一个电耦合到相应的一个存储单元，至少间接耦合到多个锁存器件中的一个，并由选择器输入端控制。 在该方法中，将负载时钟施加到多个锁存装置，使得模式被加载到多个锁存装置中。 选择器输入被断言，使得图案的导数被多个选择器接收并返回到多个锁存装置。 系统时钟被施加到多个锁存装置，使得图案的导数被加载到多个锁存装置中。

公开(公告)号：US07454946B2

公开(公告)日：2008-11-25

申请号：US11390006

申请日：2006-03-27

申请人： Jeanne Krayer Pitz ,  Ted Lekan ,  Michael Vincze

发明人： Jeanne Krayer Pitz ,  Ted Lekan ,  Michael Vincze

IPC分类号： G01P21/00

CPC分类号： G01P21/00

摘要： Systems, methods and circuits for implementing a self test in a slowly varying sensor. In one particular case, a circuit is provided that includes two filters operating in parallel. One of the filters is tailored for filtering normal operational signals, and operates at a first oversampling rate. The other filter is tailored for filtering test signals, and operates at a second oversampling rate. The second oversampling rate is generally less than the first oversampling rate. In various cases, the filter tailored for filtering normal operational signals may be programmed for operation across a plurality of oversampling rates.

摘要翻译： 用于在缓慢变化的传感器中实现自检的系统，方法和电路。 在一个特定情况下，提供了包括并联操作的两个滤波器的电路。 其中一个滤波器适用于过滤正常操作信号，并以第一过采样速率运行。 另一个滤波器是针对滤波测试信号量身定做的，并以第二次过采样率运行。 第二次过采样率通常小于第一次过采样率。 在各种情况下，用于过滤正常操作信号的过滤器可以被编程为跨多个过采样率进行操作。

公开(公告)号：US20070050437A1

公开(公告)日：2007-03-01

申请号：US11212835

申请日：2005-08-25

申请人： Jeanne Krayer Pitz ,  Ted Lekan

发明人： Jeanne Krayer Pitz ,  Ted Lekan

IPC分类号： G06F7/58

CPC分类号： G06F7/588 ,  G06J1/00

摘要： Systems, methods and circuits for generating random numbers. As one example, a system for generating random numbers is disclosed that includes an analog to digital conversion element that provides an output, and a digital filter that is electrically coupled to the analog to digital conversion element and provides an information signal based at least in part on the output. In addition, the system includes a memory device electrically coupled to a sequencer that generates a capture signal. The memory is operable to capture the information signal based at least in part on the capture signal.

摘要翻译： 用于生成随机数的系统，方法和电路。 作为一个示例，公开了一种用于产生随机数的系统，其包括提供输出的模数转换元件和电耦合到模数转换元件的数字滤波器，并至少部分地提供信息信号 在输出。 此外，该系统包括电耦合到产生捕获信号的定序器的存储器件。 存储器可操作以至少部分地基于捕获信号捕获信息信号。

公开(公告)号：US07032430B1

公开(公告)日：2006-04-25

申请号：US11147812

申请日：2005-06-07

申请人： Jeanne Krayer Pitz ,  Ted Lekan ,  Michael Vincze

发明人： Jeanne Krayer Pitz ,  Ted Lekan ,  Michael Vincze

IPC分类号： G01P21/00

CPC分类号： G01P21/00

摘要： Systems, methods and circuits for implementing a self test in a slowly varying sensor. In one particular case, a circuit is provided that includes two filters operating in parallel. One of the filters is tailored for filtering normal operational signals, and operates at a first oversampling rate. The other filter is tailored for filtering test signals, and operates at a second oversampling rate. The second oversampling rate is generally less than the first oversampling rate. In various cases, the filter tailored for filtering normal operational signals may be programmed for operation across a plurality of oversampling rates.

摘要翻译： 用于在缓慢变化的传感器中实现自检的系统，方法和电路。 在一个特定情况下，提供了包括并联操作的两个滤波器的电路。 其中一个滤波器适用于过滤正常操作信号，并以第一过采样速率运行。 另一个滤波器是针对滤波测试信号量身定做的，并以第二次过采样率运行。 第二次过采样率通常小于第一次过采样率。 在各种情况下，用于过滤正常操作信号的过滤器可以被编程为跨多个过采样率进行操作。

公开(公告)号：US06470459B1

公开(公告)日：2002-10-22

申请号：US09450822

申请日：1999-11-29

申请人： Jeanne Krayer Pitz

发明人： Jeanne Krayer Pitz

IPC分类号： G06F104

CPC分类号： G06F3/0607 ,  G06F3/0658 ,  G06F3/0674 ,  G06F13/4018

摘要： An interface circuit (10) for use in a read channel of mass data storage device and which is synchronous with a clock (CLK8) of the mass data storage device operates to receive data (12) coming into the circuit (10) controlled by an associated controller. The circuit (10) is easily configurable to process either a full word length at once, or by half-word portions. In the half-word mode, the data coming into the circuit is clocked into one of three data registers (18, 36, 38). When a flag (NZH, NZL) that indicates that data is starting is detected, the phase of the received data with respect to the clock is determined by comparing (50) the phase of the full word clock (CLK8) to the phase of a half-word clock (CLK4). If the clocks are in-phase, the first two registers (18,36) are selected to contain respective halves of the data word. If the clocks are out-of-phase, the second two registers (36,38) are selected to contain the respective halves of the data word. The word halves are directed by multiplexers to output registers (26,28) for delivery to the channel (14) of the mass data storage device.

摘要翻译： 一种在质量数据存储装置的读通道中使用并与大容量数据存储装置的时钟（CLK8）同步的接口电路（10），用于接收进入电路（10）的数据（12），该数据（12）由 关联控制器。 电路（10）可以容易地配置为一次处理一个完整的字长，也可以半字部分处理。 在半字模式中，进入电路的数据被计时到三个数据寄存器（18,36,38）之一。 当检测到指示数据开始的标志（NZH，NZL）时，通过将全字时钟（CLK8）的相位与（a）的相位相比较来确定接收数据相对于时钟的相位 半字时钟（CLK4）。 如果时钟是同相的，则前两个寄存器（18,36）被选择为包含数据字的相应两半。 如果时钟不同步，则选择第二个两个寄存器（36,38）以包含数据字的相应两半。 字半部由多路复用器引导到输出寄存器（26,28），用于传送到大容量数据存储设备的通道（14）。

公开(公告)号：US07512645B2

公开(公告)日：2009-03-31

申请号：US10804750

申请日：2004-03-19

申请人： Jeanne Krayer Pitz ,  Alexander Teutsch ,  Nicole Cunningham

发明人： Jeanne Krayer Pitz ,  Alexander Teutsch ,  Nicole Cunningham

IPC分类号： G06F1/02

CPC分类号： G06F7/584

摘要： A system that has a pseudorandom number generator and a mapping system. The pseudorandom number generator generates a random number that is mapped by the mapping system to an output value that is selected from a set of predetermined output values. To increase the randomness of the sequence of numbers generated by the pseudorandom number generator, a tap and/or seed value of the pseudorandom number generator can be varied.

摘要翻译： 具有伪随机数生成器和映射系统的系统。 伪随机数生成器生成由映射系统映射到从一组预定输出值中选择的输出值的随机数。 为了增加由伪随机数发生器产生的数字序列的随机性，可以改变伪随机数发生器的抽头和/或种子值。

公开(公告)号：US07061325B2

公开(公告)日：2006-06-13

申请号：US10749655

申请日：2003-12-31

申请人： Jeanne Krayer Pitz

发明人： Jeanne Krayer Pitz

IPC分类号： H03G3/10

CPC分类号： H03F3/45973

摘要： A system and method for providing digital compensation and correction for an amplifier. The system is configured to provide a digitally compensated representation of a first amplified analog signal indicative of a first parameter based on a digital representation of the first amplified analog signal and a digital representation of a second analog signal indicative of a second parameter. The digitally compensated representation of the first amplified analog signal is determined by applying a pre-stored compensation factor to an offset adjustment calculation for the second parameter to provide a compensated offset adjustment. The compensated offset adjustment is combined with an adjusted gain to provide an offset and gain correction for weighting the first parameter to provide the digitally compensated representation of the first parameter. The adjusted gain can be determined by applying a pre-stored gain factor data to the second parameter.

摘要翻译： 一种用于为放大器提供数字补偿和校正的系统和方法。 该系统被配置为基于第一放大模拟信号的数字表示和指示第二参数的第二模拟信号的数字表示来提供指示第一参数的第一放大模拟信号的数字补偿表示。 通过将预先存储的补偿因子应用于第二参数的偏移调整计算来确定第一放大模拟信号的数字补偿表示，以提供经补偿的偏移调整。 经补偿的偏移调整与调整的增益组合以提供偏移和增益校正，用于对第一参数进行加权以提供第一参数的数字补偿表示。 可以通过将预先存储的增益因子数据应用于第二参数来确定经调整的增益。