公开(公告)号：US07155600B2

公开(公告)日：2006-12-26

申请号：US10422648

申请日：2003-04-24

申请人： William Elton Burky ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

发明人： William Elton Burky ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/485

摘要： A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process. Then, the logic determines one or more threads to start in conformity with a thread enable state specifying the enable state of multiple threads and reallocates various resources, dividing them between threads if multiple threads are specified for further execution (multi-threaded mode) or allocating substantially all of the resources to a single thread if further execution is specified as single-threaded mode. The processor then starts execution of the remaining enabled threads.

摘要翻译： 用于在同时多线程（SMT）处理器中的单线程和多线程执行状态之间切换的方法和逻辑设备提供了在单线程和多线程执行之间进行切换的机制。 处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。 内部控制逻辑控制结束指令预取，调度新指令，中断处理和维护操作的事件序列，并等待处理器的操作完成以处理正在进行的指令。 然后，逻辑根据指定多个线程的使能状态的线程使能状态确定一个或多个线程，以重新分配各种资源，如果多个线程被指定用于进一步执行（多线程模式）或分配 如果进一步执行被指定为单线程模式，则基本上所有的资源到单个线程。 然后，处理器开始执行剩余的已启用线程。

公开(公告)号：US20100250900A1

公开(公告)日：2010-09-30

申请号：US12409934

申请日：2009-03-24

申请人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3814 ,  G06F9/3838

摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.

摘要翻译： 信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。 映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。 在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

公开(公告)号：US08086826B2

公开(公告)日：2011-12-27

申请号：US12409934

申请日：2009-03-24

申请人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/38 ,  G06F9/52

CPC分类号： G06F9/3814 ,  G06F9/3838

摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.

摘要翻译： 信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。 映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。 在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

公开(公告)号：US08103852B2

公开(公告)日：2012-01-24

申请号：US12342045

申请日：2008-12-22

申请人： James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Todd Alan Venton

发明人： James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Todd Alan Venton

IPC分类号： G06F15/76

CPC分类号： G06F9/30043 ,  G06F9/3838

摘要： An information handling system includes a processor with a bifurcated unified issue queue that may perform unified issue queue VSU store instruction dependency operations. The bifurcated unified issue queue BUIQ maintains VSU store instructions in the form of internal operations data. The BUIQ includes a unified issue queue UIQ 0 and a unified issue queue UIQ 1. The BUIQ may manage a particular VSU store instruction from one UIQ to determine data dependencies and employ the other UIQ to determine address dependencies of that particular VSU store instruction. The UIQs employ a dependency matrix including a dependency array. The dependency array data maintains both data and address dependency information. The particular VSU store instruction issues to execution units such as VSUs for data dependency information and load store units (LSUs) for address dependency information. A particular VSU store instruction may execute to provide data dependency information independent of address dependency information.

摘要翻译： 信息处理系统包括具有分叉的统一发布队列的处理器，其可以执行统一的发布队列VSU存储指令依赖性操作。 分叉统一问题队列BUIQ以内部操作数据的形式维护VSU存储指令。 BUIQ包括统一的问题队列UIQ 0和统一的问题队列UIQ 1. BUIQ可以管理来自一个UIQ的特定VSU存储指令以确定数据依赖性并且使用另一个UIQ来确定该特定VSU存储指令的地址依赖性。 UIQ采用包括依赖性数组的依赖矩阵。 依赖性阵列数据维护数据和地址相关性信息。 特定的VSU存储指令发送到执行单元，例如用于数据依赖性信息的VSU和用于地址依赖性信息的加载存储单元（LSU）。 可以执行特定的VSU存储指令以提供独立于地址依赖性信息的数据依赖性信息。

公开(公告)号：US07380104B2

公开(公告)日：2008-05-27

申请号：US11380078

申请日：2006-04-25

申请人： William Elton Burky ,  Raymond Cheung Yeung

发明人： William Elton Burky ,  Raymond Cheung Yeung

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/3836 ,  G06F9/3838

摘要： A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more instructions in the queue are evaluated to determine if any of them are dependent on the designated instruction. For the evaluation, each instruction placed into the queue is accompanied by corresponding logic elements that provide destination to source compares for the instruction. In an embodiment comprising a method, the oldest ready instruction in the queue during a particular cycle is identified. When an instruction was previously designated to issue during the particular cycle, it is determined whether at least a first instruction in the queue complies with each condition in a set of conditions, the set including at least the conditions that the first instruction has a dependency on the designated instruction, and that the first instruction is older than the oldest ready instruction. The first instruction is selected for issue during the next following cycle only if the first instruction complies with each condition in the set.

摘要翻译： 提供了一种用于在队列的特定周期期间评估出故障发送队列中的两个或更多个指令的方法，以在下一个后续周期中选择要发出的指令。 如果先前指定在特定周期内发出指令，则会对队列中的一个或多个指令进行评估，以确定其中任何一个是否依赖于指定的指令。 对于评估，放置到队列中的每条指令都伴随有相应的逻辑元素，为指令提供目标到源的比较。 在包括方法的实施例中，识别在特定周期期间队列中最早的就绪指令。 当先前指定在特定周期期间发出指令时，确定队列中的至少第一指令是否符合一组条件中的每个条件，该集合至少包括第一指令依赖于的条件 指定的指令，并且第一条指令比最早的就绪指令更旧。 仅当第一条指令符合该组中的每个条件时，才在下一个后续周期中选择第一条指令进行发布。

公开(公告)号：US07266675B2

公开(公告)日：2007-09-04

申请号：US11324399

申请日：2006-01-03

申请人： William Elton Burky ,  Peter Juergen Klim

发明人： William Elton Burky ,  Peter Juergen Klim

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： A processor including a register file and method for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the column having an index equal to the row selector is automatically reset (excepting the absent cell mentioned above) . On a read of a row, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag.

摘要翻译： 包括用于在多线程处理系统中计算闪存掩码的寄存器文件和方法的处理器响应于多个刷新请求源而提供刷新结果的快速和低逻辑开销计算。 刷新掩码寄存器文件由数组中的多个单元格实现，其中单元格不在对角线，其中列索引等于行索引。 每个单元都具有垂直写入使能和水平写入使能。 当写入一行以验证该行的标签值时，具有等于行选择器的索引的列将自动重置（除了上述缺少的单元格）。 在读取一行时，每列提供的有线AND电路提供了与上一次重置行之后写入的其他行相对应的位字段，该行是指示较新标签和所选标签的刷新掩码。

公开(公告)号：US07010750B2

公开(公告)日：2006-03-07

申请号：US09931298

申请日：2001-08-16

申请人： William Elton Burky

发明人： William Elton Burky

IPC分类号： G06F15/00

CPC分类号： G06F17/211

摘要： A data processing system (10) has a processor (11), a display device (15), and a user input arrangement (17) which includes a pointer control device (19) such as a mouse. An edit function input is entered through the user input arrangement (17) and a target to be edited is identified in response to the edit function input. The target comprises some displayed object that is specified by proximity to a system pointer (29) at the time the edit function input is received. The edit function input defines an edit operation to be performed by the data processing system (10) on the identified target. After receiving the edit function input and responding to the input by identifying the target, the method includes determining a state of the target which indicates whether or not the edit operation is currently applied to the target. If the state of the target indicates that the edit operation is not currently applied to the target, the method includes applying the edit operation to the target. In this way, the edit operation is applied to the target without first having to explicitly select the target.

摘要翻译： 数据处理系统（10）具有处理器（11），显示装置（15）和包括诸如鼠标的指针控制装置（19）的用户输入装置（17）。 通过用户输入装置（17）输入编辑功能输入，并且响应于编辑功能输入识别要编辑的目标。 目标包括在接收编辑功能输入时由接近系统指针（29）指定的一些显示对象。 编辑功能输入定义要由所识别的目标由数据处理系统（10）执行的编辑操作。 在接收到编辑功能输入并通过识别目标来响应输入之后，该方法包括确定目标的状态，该状态指示当前是否对目标应用编辑操作。 如果目标的状态表示编辑操作当前未被应用于目标，则该方法包括将编辑操作应用于目标。 以这种方式，编辑操作被应用于目标，而不必首先必须明确地选择目标。

公开(公告)号：US06430680B1

公开(公告)日：2002-08-06

申请号：US09052567

申请日：1998-03-31

申请人： William Elton Burky ,  David Andrew Schroter ,  Shih-Hsiung Stephen Tung ,  Michael Thomas Vaden

发明人： William Elton Burky ,  David Andrew Schroter ,  Shih-Hsiung Stephen Tung ,  Michael Thomas Vaden

IPC分类号： G06F900

CPC分类号： G06F9/3455 ,  G06F9/3832

摘要： A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.

摘要翻译： 公开了一种在数据处理系统内取出数据的处理器和方法。 根据该方法，计算第一加载地址和第二加载地址之间的第一差。 此外，确定第三加载地址和第二加载地址之间的第二差是否等于第一差。 响应于确定第一差异和第二差异相等，通过将第三地址和第二差值相加产生的第四加载地址作为存储器提取地址被发送到存储器。 在包括具有关联高速缓存的处理器的数据处理系统的实施例中，仅当第四加载地址不驻留在高速缓存中或未完成的存储器提取请求的目标时才将第四加载地址发送到存储器。

公开(公告)号：US07769986B2

公开(公告)日：2010-08-03

申请号：US11742905

申请日：2007-05-01

申请人： Christopher Michael Abernathy ,  William Elton Burky ,  Jens Leenstra ,  Nicolas Maeding

发明人： Christopher Michael Abernathy ,  William Elton Burky ,  Jens Leenstra ,  Nicolas Maeding

IPC分类号： G06F12/00

CPC分类号： G06F9/3836 ,  G06F9/3804 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A method and apparatus for register renaming are provides in the illustrative embodiments. A mapper receives a request for a data in a logical register. The mapper searches an in-flight map table and a set of architected map tables for the data in the logical register. The mapper identifies an entry in one of the in-flight map table and an architected map table in the set of architected map tables that corresponds with the logical register in the request. The mapper returns a location of a physical register, which holds the requested data.

摘要翻译： 在说明性实施例中提供了用于寄存器重命名的方法和装置。 映射器接收对逻辑寄存器中的数据的请求。 映射器搜索逻辑寄存器中的数据的飞行中地图表和一组架构图。 映射器在飞行中的映射表之一中标识一个条目，并在与该请求中的逻辑寄存器对应的一组架构映射表中的架构映射表中。 映射器返回一个物理寄存器的位置，它保存所请求的数据。

公开(公告)号：US20080276076A1

公开(公告)日：2008-11-06

申请号：US11742905

申请日：2007-05-01

申请人： Christopher Michael Abernathy ,  William Elton Burky ,  Jens Leenstra ,  Nicolas Maeding

发明人： Christopher Michael Abernathy ,  William Elton Burky ,  Jens Leenstra ,  Nicolas Maeding

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3804 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A method and apparatus for register renaming are provides in the illustrative embodiments. A mapper receives a request for a data in a logical register. The mapper searches an in-flight map table and a set of architected map tables for the data in the logical register. The mapper identifies an entry in one of the in-flight map table and an architected map table in the set of architected map tables that corresponds with the logical register in the request. The mapper returns a location of a physical register, which holds the requested data.

摘要翻译： 在说明性实施例中提供了用于寄存器重命名的方法和装置。 映射器接收对逻辑寄存器中的数据的请求。 映射器搜索逻辑寄存器中的数据的飞行中地图表和一组架构图。 映射器在飞行中的映射表之一中标识一个条目，并在与该请求中的逻辑寄存器对应的一组架构映射表中的架构映射表中。 映射器返回一个物理寄存器的位置，它保存所请求的数据。