公开(公告)号：US20100250900A1

公开(公告)日：2010-09-30

申请号：US12409934

申请日：2009-03-24

申请人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3814 ,  G06F9/3838

摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.

摘要翻译： 信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。 映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。 在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

公开(公告)号：US08086826B2

公开(公告)日：2011-12-27

申请号：US12409934

申请日：2009-03-24

申请人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Mary Douglass Brown ,  William Elton Burky ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/38 ,  G06F9/52

CPC分类号： G06F9/3814 ,  G06F9/3838

摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.

摘要翻译： 信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。 映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。 在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

公开(公告)号：US08108655B2

公开(公告)日：2012-01-31

申请号：US12410073

申请日：2009-03-24

申请人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

发明人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

IPC分类号： G06F9/302 ,  G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3885

摘要： Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.

摘要翻译： 问题逻辑标识一个简单的固定点指令，包含在一个准备发布的统一有效载荷中。 简单的固定点指令是一种可由固定点执行单元和加载存储执行单元执行的指令。 反过来，问题逻辑确定统一有效载荷不包括准备发布的加载存储指令。 结果，响应于确定简单的固定点指令准备发出并且确定统一的有效载荷不包括加载存储指令，问题逻辑将简单的固定点指令发布到加载存储执行单元 准备发行。

公开(公告)号：US20100250901A1

公开(公告)日：2010-09-30

申请号：US12410073

申请日：2009-03-24

申请人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

发明人： Christopher Michael Abernathy ,  James Wilson Bishop ,  Mary Douglass Brown ,  William Elton Burky ,  Robert Allen Cordes ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Todd Alan Venton

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3885

摘要： Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.

摘要翻译： 问题逻辑标识一个简单的固定点指令，包含在一个准备发布的统一有效载荷中。 简单的固定点指令是一种可由固定点执行单元和加载存储执行单元执行的指令。 反过来，问题逻辑确定统一有效载荷不包括准备发布的加载存储指令。 结果，响应于确定简单的固定点指令准备发出并且确定统一的有效载荷不包括加载存储指令，问题逻辑将简单的固定点指令发布到加载存储执行单元 准备发行。

公开(公告)号：US07290261B2

公开(公告)日：2007-10-30

申请号：US10422651

申请日：2003-04-24

申请人： William Elton Burky ,  Bjorn Peter Christensen ,  Dung Quoc Nguyen ,  David A. Schroter ,  Albert Thomas Williams

发明人： William Elton Burky ,  Bjorn Peter Christensen ,  Dung Quoc Nguyen ,  David A. Schroter ,  Albert Thomas Williams

IPC分类号： G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/384

摘要： A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. When switching from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, “dummy” instruction group dispatch indications are sent to the mapper that indicate use of all architected registers for each thread.

摘要翻译： 电路和方法为同时多线程（SMT）处理器提供重命名寄存器重新分配，该处理器在单线程（ST）执行期间的一个线程和多线程执行期间的多个线程之间重新分配重命名（映射）资源。 处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。 内部控制逻辑然后发出资源重新分配资源。 重命名资源通过在重命名映射器处指示一个动作来重新分配。 当从SMT切换到ST模式时，映射器被定向到垂死线程的条目，但是在从ST到SMT模式的切换中，将“伪”指令组分派指示发送到映射器，指示使用所有架构的寄存器 每个线程。

公开(公告)号：US06275918B1

公开(公告)日：2001-08-14

申请号：US09268307

申请日：1999-03-16

申请人： William Elton Burky ,  Peter Steven Lenk ,  Dung Quoc Nguyen ,  David Andrew Schroter ,  Shih-Hsiung Stephen Tung ,  Michael Thomas Vaden

发明人： William Elton Burky ,  Peter Steven Lenk ,  Dung Quoc Nguyen ,  David Andrew Schroter ,  Shih-Hsiung Stephen Tung ,  Michael Thomas Vaden

IPC分类号： G06F934

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3832

摘要： A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.

摘要翻译： 公开了一种利用预取历史表改善数据处理系统中的预取精度的方法和系统。 该方法基于条目中包含的有效位的状态，将指令地址的一部分与位于预取历史表中的条目的地址进行比较。 如果有效位被设置并且地址匹配，则检查条目内的指示符字段以查看其是否等于或大于阈值级别。 当指示符字段大于阈值电平时，将根据步幅和方向预取目标操作数地址。

公开(公告)号：US08418180B2

公开(公告)日：2013-04-09

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。 在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US20080250226A1

公开(公告)日：2008-10-09

申请号：US11696363

申请日：2007-04-04

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885

摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.

摘要翻译： 多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。 响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。 当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。 如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

公开(公告)号：US20080229065A1

公开(公告)日：2008-09-18

申请号：US11685428

申请日：2007-03-13

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5061 ,  G06F2209/5012

摘要： A configurable microprocessor which combines a plurality of corelets into a single microprocessor core to handle high computing-intensive workloads. The process first selects two or more corelets in the plurality of corelets. The process combines resources of the two or more corelets to form combined resources, wherein each combined resource comprises a larger amount of a resource available to each individual corelet. The process then forms a single microprocessor core from the two or more corelets by assigning the combined resources to the single microprocessor core, wherein the combined resources are dedicated to the single microprocessor core, and wherein the single microprocessor core processes instructions with the dedicated combined resources.

摘要翻译： 一种可配置的微处理器，将多个核心组合成单个微处理器核心，以处理高计算密集型工作负载。 该过程首先在多个核心中选择两个或更多个核心。 该过程组合两个或更多个核心小区的资源以形成组合的资源，其中每个组合的资源包括更大量的可用于每个单个小堆的资源。 然后，该过程通过将组合的资源分配给单个微处理器核心而从两个或更多个核心小区形成单个微处理器核心，其中组合资源专用于单个微处理器核心，并且其中单个微处理器核心使用专用组合资源来处理指令 。

公开(公告)号：US08380964B2

公开(公告)日：2013-02-19

申请号：US12417878

申请日：2009-04-03

申请人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

发明人： James Wilson Bishop ,  Mary Douglass Brown ,  Jeffrey Carl Brownscheidle ,  Robert Allen Cordes ,  Maureen Anne Delaney ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Joel Abraham Silberman

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC分类号： G06F9/3855

摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.

摘要翻译： 信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。 问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。 年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。 在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。 年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。 问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。