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公开(公告)号：US07047179B2
公开(公告)日：2006-05-16
申请号：US10459340
申请日：2003-06-11
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.
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公开(公告)号：US06618698B1
公开(公告)日：2003-09-09
申请号：US09373125
申请日：1999-08-12
IPC分类号： G06F9455
CPC分类号： G06F17/5027
摘要： Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.
摘要翻译： 处理器集群作为仿真引擎互连，使得处理器共享输入和数据堆栈，并行地完成结果的设置和存储，但是一个评估单元的输出连接到下一个评估单元的输入。 一组“级联”连接提供对中间值的访问。通过点击一个处理器的中间值，并将它们馈送到下一个处理器，可以实现显着的仿真加速。
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3.发明授权High speed software driven emulator comprised of a plurality of emulation processors with a method to allow memory read/writes without interrupting the emulation 有权高速软件驱动的仿真器由多个仿真处理器组成，具有允许存储器读/写而不中断仿真的方法公开(公告)号：US07089538B1
公开(公告)日：2006-08-08
申请号：US09655596
申请日：2000-09-06
申请人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
发明人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
IPC分类号： G06F9/44
CPC分类号： G06F17/5022
摘要： A software driven emulator in which the stored emulation program for a processor module is compiled to include a code bit or bits in the emulation instruction step sequence that is decoded as main data memory disable command. Thus, once in each emulation program cycle, the memory controller disables the main data memories on the module, and allows the maintenance bus to read or write data to these memories.
摘要翻译： 一种软件驱动的仿真器，其中存储用于处理器模块的存储的仿真程序被编译为包括被解码为主数据存储器禁止命令的仿真指令步骤序列中的代码位或位。 因此，在每个仿真程序周期中，存储器控制器禁用模块上的主数据存储器，并允许维护总线读取或写入数据到这些存储器。
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4.发明授权High speed software driven emulator comprised of a plurality of emulation processors with improved multiplexed data memory 有权由具有改进的多路复用数据存储器的多个仿真处理器组成的高速软件驱动的仿真器公开(公告)号：US07043417B1
公开(公告)日：2006-05-09
申请号：US09656146
申请日：2000-09-06
申请人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
发明人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
CPC分类号： G06F13/1647
摘要： In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.
摘要翻译： 在仿真器处理器集群中，共享输入和数据存储器堆栈的读取端口被时间复用以服务于多个处理器。 在本发明的示例性实施例中，256x8存储器阵列用作簇中四个处理器的共享存储器。 两个读端口在集群中的四个处理器之间进行时间复用。 在一个读取周期中，来自两个读取端口的数据耦合到两个处理器。 下一个读取周期将数据从相同的两个端口读取到剩余的两个处理器。 在优选实施例中，存储器以系统时钟速度的两倍运行，使得整体仿真处理执行时间不受影响。
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5.发明授权公开(公告)号：US07107203B1
公开(公告)日：2006-09-12
申请号：US09655595
申请日：2000-09-06
申请人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
发明人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
CPC分类号： G06F17/5027
摘要： A system and method for determining which of several possible cable lengths has been used by reversing the end-to-end correspondence of at least two conductors in the cable. A different two conductors are selected to identify respective different cable lengths. Each input pin is connected to a correspondingly identified output pin, except for the pair with the outputs reversed, which pair signifies the cable length.
摘要翻译： 通过反转电缆中的至少两个导体的端对端对应来确定已经使用几种可能的电缆长度中的哪一种的系统和方法。 选择不同的两个导体来识别相应的不同的电缆长度。 每个输入引脚连接到相应识别的输出引脚，除了反向输出的输出引脚之外，这对引脚指示电缆长度。
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6.发明授权High speed software driven emulator comprised of a plurality of emulation processors with a method to allow high speed bulk read/write operation synchronous DRAM while refreshing the memory 有权高速软件驱动的仿真器包括多个仿真处理器，其具有允许高速大容量读/写操作同步DRAM同时刷新存储器的方法公开(公告)号：US06901359B1
公开(公告)日：2005-05-31
申请号：US09656541
申请日：2000-09-06
申请人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
发明人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
CPC分类号： G06F13/1615 , G06F17/5027
摘要： A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.
摘要翻译： 用于批量传输到SRAM的系统和方法，其中开始存储器地址被锁存，然后每个时钟周期递增，以产生新的存储器地址。 地址被解码，并且存储器请求被流水线到SRAM存储器，每个时钟周期一个。 当存储器控制器检测到预定数量的时钟周期或字（例如64字或四个时钟周期）的边界的传送时，数据传输的突发模式被停止，并且存储器控制器在恢复另一个周期之前等待“完成”信号 的突发传输模式。 存储器控制器在该地址边界上检测请求首先进行存储器刷新，然后进行所请求的操作; 例如 转移操作的延续。
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7.发明授权High speed software driven emulator comprised of a plurality of emulation processors with an improved maintenance bus that streams data at high speed 有权由具有改进的维护总线的多个仿真处理器组成的高速软件驱动的仿真器，其以高速度传输数据公开(公告)号：US06850880B1
公开(公告)日：2005-02-01
申请号：US09656147
申请日：2000-09-06
申请人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
发明人： William F. Beausoleil , R. Bryan Cook , Tak-kwong Ng , Helmut Roth , Peter Tannenbaum , Lawrence A. Thomas , Norton J. Tomassetti
CPC分类号： G06F17/5027
摘要： A software driven emulator has a maintenance bus operating protocol mode in which, after an initial address phase, data is streamed continuously by automatically incrementing the sending and receiving addresses.
摘要翻译： 软件驱动的仿真器具有维护总线操作协议模式，其中在初始地址相位之后，通过自动递增发送和接收地址来连续流式传输数据。
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公开(公告)号：US07738398B2
公开(公告)日：2010-06-15
申请号：US10992165
申请日：2004-11-17
IPC分类号： H04L12/28
CPC分类号： G06F17/5027 , H04L25/0272
摘要： An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.
摘要翻译： 用于识别和验证通信系统的选定组件的识别系统及其制造和使用方法。 通信系统包括被配置为与一个或多个目标系统耦合的主机系统。 当主机系统与所选择的目标系统耦合时，通信系统可以进入识别模式，其中所选择的目标系统可以向主机系统提供识别数据。 识别数据包括关于与所选择的目标系统相关联的至少一个目标系统特征的信息，使得主机系统可以至少部分地基于目标系统特性来尝试识别所选择的目标系统。 一旦所选择的目标系统被识别，通信系统同样可以根据需要至少部分地重新配置主机系统，使得主机系统可以与所选择的目标系统兼容。
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公开(公告)号：US07738399B2
公开(公告)日：2010-06-15
申请号：US10992588
申请日：2004-11-17
IPC分类号： H04L12/28
CPC分类号： H04L41/0803 , H04L41/0866 , H04L41/145
摘要： An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.
摘要翻译： 用于识别和验证通信系统的选定组件的识别系统及其制造和使用方法。 通信系统包括被配置为与一个或多个目标系统耦合的主机系统。 当主机系统与所选择的目标系统耦合时，通信系统可以进入识别模式，其中所选择的目标系统可以向主机系统提供识别数据。 识别数据包括关于与所选择的目标系统相关联的至少一个目标系统特征的信息，使得主机系统可以至少部分地基于目标系统特性来尝试识别所选择的目标系统。 一旦所选择的目标系统被识别，通信系统同样可以根据需要至少部分地重新配置主机系统，使得主机系统可以与所选择的目标系统兼容。
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公开(公告)号：US20050271078A1
公开(公告)日：2005-12-08
申请号：US10992165
申请日：2004-11-17
CPC分类号： G06F17/5027 , H04L25/0272
摘要： An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.
摘要翻译： 用于识别和验证通信系统的选定组件的识别系统及其制造和使用方法。 通信系统包括被配置为与一个或多个目标系统耦合的主机系统。 当主机系统与所选择的目标系统耦合时，通信系统可以进入识别模式，其中所选择的目标系统可以向主机系统提供识别数据。 识别数据包括关于与所选择的目标系统相关联的至少一个目标系统特征的信息，使得主机系统可以至少部分地基于目标系统特性来尝试识别所选择的目标系统。 一旦所选择的目标系统被识别，通信系统同样可以根据需要至少部分地重新配置主机系统，使得主机系统可以与所选择的目标系统兼容。
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