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公开(公告)号：US07738399B2
公开(公告)日：2010-06-15
申请号：US10992588
申请日：2004-11-17
IPC分类号： H04L12/28
CPC分类号： H04L41/0803 , H04L41/0866 , H04L41/145
摘要： An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.
摘要翻译： 用于识别和验证通信系统的选定组件的识别系统及其制造和使用方法。 通信系统包括被配置为与一个或多个目标系统耦合的主机系统。 当主机系统与所选择的目标系统耦合时，通信系统可以进入识别模式，其中所选择的目标系统可以向主机系统提供识别数据。 识别数据包括关于与所选择的目标系统相关联的至少一个目标系统特征的信息，使得主机系统可以至少部分地基于目标系统特性来尝试识别所选择的目标系统。 一旦所选择的目标系统被识别，通信系统同样可以根据需要至少部分地重新配置主机系统，使得主机系统可以与所选择的目标系统兼容。
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公开(公告)号：US07738398B2
公开(公告)日：2010-06-15
申请号：US10992165
申请日：2004-11-17
IPC分类号： H04L12/28
CPC分类号： G06F17/5027 , H04L25/0272
摘要： An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.
摘要翻译： 用于识别和验证通信系统的选定组件的识别系统及其制造和使用方法。 通信系统包括被配置为与一个或多个目标系统耦合的主机系统。 当主机系统与所选择的目标系统耦合时，通信系统可以进入识别模式，其中所选择的目标系统可以向主机系统提供识别数据。 识别数据包括关于与所选择的目标系统相关联的至少一个目标系统特征的信息，使得主机系统可以至少部分地基于目标系统特性来尝试识别所选择的目标系统。 一旦所选择的目标系统被识别，通信系统同样可以根据需要至少部分地重新配置主机系统，使得主机系统可以与所选择的目标系统兼容。
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3.发明授权Emulation system with improved reliability of interconnect and a method for programming such interconnect 有权具有改进的互连可靠性的仿真系统和用于编程这种互连的方法公开(公告)号：US08959010B1
公开(公告)日：2015-02-17
申请号：US13315161
申请日：2011-12-08
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： A method and apparatus for redundant communication channels in an emulation system is disclosed. A processor-based emulation system has a plurality of emulation chips on an emulation board. The emulation chips have a plurality of processor clusters. Signals are sent over one or more communication channels between processor clusters, including from a processor cluster on one emulation chip to a processor cluster on another emulation chip. Copies of the same signal may be sent in duplicate over separate communication channels. If a communication channel failure is detected, instruction memory is modified so that a processor cluster's instructions no longer address a first cluster memory location, but instead address a second cluster memory location of a non-failed communication channel. By using redundant communication channels, emulation system interconnect reliability is increased and recompilation of the design under verification may be avoided.
摘要翻译： 公开了一种用于仿真系统中的冗余通信信道的方法和装置。 基于处理器的仿真系统在仿真板上具有多个仿真芯片。 仿真芯片具有多个处理器集群。 信号通过处理器集群之间的一个或多个通信信道发送，包括从一个仿真芯片上的处理器集群到另一个仿真芯片上的处理器集群。 相同信号的副本可以通过单独的通信信道重复发送。 如果检测到通信信道故障，则修改指令存储器，使得处理器集群的指令不再解决第一集群存储器位置，而是寻址非故障通信信道的第二集群存储器位置。 通过使用冗余通信通道，可以提高仿真系统互连的可靠性，并且可以避免验证设计的重新编译。
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公开(公告)号：US08296121B2
公开(公告)日：2012-10-23
申请号：US11789677
申请日：2007-04-25
IPC分类号： G06F9/455 , G06F1/00 , G06G7/54 , G01K1/00 , G01K3/00 , G01K5/00 , G01K7/00 , G01K9/00 , G01K11/00 , G01K1/08 , G01K13/00 , G01K17/00
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/3296 , G06F2200/201 , Y02D10/16 , Y02D10/172
摘要： Method and apparatus for controlling power in an emulation system are described. In one example, a first interface is configured to receive requirement information for a logic module to be emulated from a host computer system. The requirement information includes at least one of a power requirement or a thermal requirement. A second interface is configured to receive measurement data from sensors in the emulation system. A controller is configured to control at least one of a synchronization system, a power regulation system, or a thermal system in the emulation system in response to the requirement information and the measurement data to reduce power load of the emulation system.
摘要翻译： 描述了用于在仿真系统中控制功率的方法和装置。 在一个示例中，第一接口被配置为接收要从主计算机系统仿真的逻辑模块的需求信息。 需求信息包括功率需求或热要求中的至少一个。 第二接口被配置为从仿真系统中的传感器接收测量数据。 控制器被配置为响应于需求信息和测量数据来控制仿真系统中的同步系统，功率调节系统或热系统中的至少一个，以减少仿真系统的功率负载。
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5.发明授权Method and apparatus for sharing data between discrete clusters of processors 有权用于在离散的处理器群集之间共享数据的方法和装置公开(公告)号：US07606698B1
公开(公告)日：2009-10-20
申请号：US11526967
申请日：2006-09-26
IPC分类号： G06F9/455
CPC分类号： G06F17/5022 , G06F17/5027
摘要： A method and apparatus for sharing data between processors within first and second discrete clusters of processors. The method comprises supplying a first amount of data from a first data array in a first discrete cluster of processors to selector logic. A second amount of data from a second data array in a second discrete cluster of processors is also supplied to the selector logic. The first or second amount of data is then selected using the selector logic, and supplied to a shared input port on a processor in the first discrete cluster of processors. The apparatus comprises selector logic for selecting between input data supplied by a first data array and a second data array. The data arrays are located within different discrete clusters of processors. The selected data is then supplied to a shared input port on a processor.
摘要翻译： 一种用于在处理器的第一和第二离散簇内的处理器之间共享数据的方法和装置。 该方法包括从处理器的第一离散簇中的第一数据阵列向选择器逻辑提供第一数据量。 来自处理器的第二离散簇中的第二数据阵列的第二数据量也被提供给选择器逻辑。 然后使用选择器逻辑来选择第一或第二数据量，并将其提供给处理器的第一离散簇中的处理器上的共享输入端口。 该装置包括用于在由第一数据阵列提供的输入数据和第二数据阵列之间进行选择的选择器逻辑。 数据阵列位于不同离散的处理器群集中。 然后将所选数据提供给处理器上的共享输入端口。
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6.发明申请Method and apparatus for synchronizing processors in a hardware emulation system 有权用于在硬件仿真系统中同步处理器的方法和装置公开(公告)号：US20070282589A1
公开(公告)日：2007-12-06
申请号：US11444032
申请日：2006-05-31
IPC分类号： G06F9/455
CPC分类号： G06F11/261 , G06F17/5027
摘要： A method, apparatus and method for compiling a hardware design for performing hardware emulation using synchronized processors is described. The apparatus comprises a plurality of processors defining a processor group for evaluating data regarding a hardware design and a synchronizer for synchronizing the operation of the processor group while emulating at least a portion of the hardware design. The method comprises providing a synchronization signal to a plurality of processors defining a processor group for evaluating data regarding a hardware design, receiving a ready signal from the processor group, and providing an execution signal to the processor group, where the execution signal causes the processor group to evaluate a submodel. The method for compiling the hardware design comprises converting at least one high-level construct into a sequence of operations and identifying a sequence of operations that comprise at least one conditional submodel.
摘要翻译： 描述了使用同步处理器来编译用于执行硬件仿真的硬件设计的方法，装置和方法。 该设备包括多个处理器，其定义用于评估关于硬件设计的数据的处理器组，以及用于在模拟硬件设计的至少一部分的同时处理器组的操作的同步器。 该方法包括向定义用于评估关于硬件设计的数据的处理器组的多个处理器提供同步信号，从处理器组接收就绪信号，以及向处理器组提供执行信号，其中执行信号使处理器 组来评估子模型。 用于编译硬件设计的方法包括将至少一个高级构造转换成操作序列并且识别包括至少一个条件子模型的操作序列。
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公开(公告)号：US08612201B2
公开(公告)日：2013-12-17
申请号：US11401641
申请日：2006-04-11
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： A hardware emulation system having a heterogeneous cluster of processors is described. The apparatus for emulating a hardware design comprises a plurality of processors, where each processor performs a different function during an emulation cycle. The method performed by the apparatus comprises using a data fetch processor to retrieve data from a data array, evaluating the retrieved data using the data fetch processor to produce an output bit, supplying the output bit to an intracluster crossbar and using a data store processor to store the output bit in the data array.
摘要翻译： 描述了具有异构的处理器簇的硬件仿真系统。 用于模拟硬件设计的装置包括多个处理器，其中每个处理器在仿真周期期间执行不同的功能。 由该装置执行的方法包括使用数据提取处理器从数据阵列中检索数据，使用数据获取处理器评估所检索的数据以产生输出比特，将输出比特提供给群内交叉开关并使用数据存储处理器 将输出位存储在数据数组中。
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8.发明申请公开(公告)号：US20100318345A1
公开(公告)日：2010-12-16
申请号：US12814337
申请日：2010-06-11
CPC分类号： G06F17/5022 , G06F11/261 , G06F17/5027 , G06F17/5045
摘要： A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus arid an emulator chip, the emulator chip includes: an emulation processor that generates emulation data, and a data array connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein simulation acceleration data from the host workstation are written to the data array of the emulator chip using the system bus.
摘要翻译： 用于将模拟加速数据从主机工作站写入硬件仿真系统的系统和方法，而不会极大地牺牲仿真速度或牺牲用户逻辑设计可用的仿真能力。 根据一个实施例，系统包括在主机工作站上运行的逻辑软件模拟器; 具有系统总线和仿真器芯片的硬件仿真系统，仿真器芯片包括：产生仿真数据的仿真处理器和连接到系统总线的数据阵列; 以及将主机工作站连接到硬件仿真器的系统总线的高速接口，其中使用系统总线将来自主机工作站的仿真加速数据写入仿真器芯片的数据阵列。
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公开(公告)号：US07606697B2
公开(公告)日：2009-10-20
申请号：US11141141
申请日：2005-05-31
申请人： Mitchell G. Poplack , John A. Maher
发明人： Mitchell G. Poplack , John A. Maher
CPC分类号： G06F11/261
摘要： A signal conversion system for interfacing selected components of a communication system and methods for manufacturing and using same. The signal conversion system converts selected logic signals from one system component into a pair of differential logic signals and provides the pair of differential logic signals to a second system component, resolving any logical and/or temporal artifacts. While one or more of the selected logic signals change signal state, the signal conversion system maintains the pair of differential logic signals in a first valid combined signal state until the signal state of the selected logic signals corresponds to a second valid combined signal state for the pair of differential logic signals. The signal verification system then updates the pair of differential logic signals to have the second valid combined signal state. The system components thereby can communicate, exchanging differential communication signals while maintaining duty cycle and avoiding signaling glitches.
摘要翻译： 一种用于连接通信系统的选定组件的信号转换系统及其制造和使用方法。 信号转换系统将所选逻辑信号从一个系统组件转换成一对差分逻辑信号，并将一对差分逻辑信号提供给第二系统组件，以解决任何逻辑和/或时间假象。 当所选逻辑信号中的一个或多个改变信号状态时，信号转换系统将该对差分逻辑信号维持在第一有效组合信号状态，直到所选逻辑信号的信号状态对应于第二有效组合信号状态 差分逻辑信号对。 信号验证系统然后更新该对差分逻辑信号以具有第二有效组合信号状态。 因此，系统组件可以通信，交换差分通信信号，同时保持占空比并避免信令故障。
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10.发明申请公开(公告)号：US20100318952A1
公开(公告)日：2010-12-16
申请号：US12814333
申请日：2010-06-11
申请人： Mitchell G. Poplack
发明人： Mitchell G. Poplack
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F17/5027 , G06F17/5045
摘要： A system and method for verifying logic circuit designs having arithmetic operations and complex logical operations such that the operations may be evaluated at substantially full hardware speed is disclosed. According to one embodiment, a system for verifying the functionalities of an electronic circuit design comprises hardware emulation resources emulating at least a portion of an electronic circuit design; and a first hardware ALU block having an arithmetic logic unit that performs an arithmetic operation or a complex logical operation of the electronic circuit design, and a set of flag registers that contains a conditional value for enabling the arithmetic logic unit.
摘要翻译： 公开了一种用于验证具有算术运算和复杂逻辑运算的逻辑电路设计的系统和方法，使得可以以基本上全硬件速度来评估操作。 根据一个实施例，用于验证电子电路设计的功能的系统包括模拟电子电路设计的至少一部分的硬件仿真资源; 以及具有执行电子电路设计的算术运算或复杂逻辑运算的算术逻辑单元的第一硬件ALU块和包含用于使能算术逻辑单元的条件值的一组标志寄存器。
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