公开(公告)号：US20070133333A1

公开(公告)日：2007-06-14

申请号：US11297311

申请日：2005-12-08

申请人： William Hovis ,  Alan Leslie ,  Phil Paone ,  David Siljenberg ,  Salvatore Storino ,  Gregory Uhlmann

发明人： William Hovis ,  Alan Leslie ,  Phil Paone ,  David Siljenberg ,  Salvatore Storino ,  Gregory Uhlmann

IPC分类号： G11C17/18

CPC分类号： G11C17/18

摘要： An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

摘要翻译： 芯片上的eFuse参考单元提供的参考电压大于由芯片上具有未引脚eFuse的eFuse单元产生的最小电压，但小于由芯片上具有熔断eFuse的eFuse单元产生的最小电压。 参考电流流过eFuse参考电池中的电阻和非吹出eFuse，产生参考电压。 参考电压用于在eFuse单元中创建参考电流的镜像副本。 参考电流的镜像副本通过eFuse单元中的eFuse流动。 比较器接收参考电压和eFuse单元产生的电压。 比较器产生一个响应于eFuse电池与参考电压相比产生的电压的输出逻辑电平。

公开(公告)号：US20080102627A1

公开(公告)日：2008-05-01

申请号：US11876230

申请日：2007-10-22

申请人： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

发明人： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L29/458 ,  H01L29/785

摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

公开(公告)号：US20060109726A1

公开(公告)日：2006-05-25

申请号：US10994087

申请日：2004-11-19

申请人： William Cochran ,  William Hovis

发明人： William Cochran ,  William Hovis

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C11/401 ,  G11C29/18

摘要： A method, apparatus, and computer program product are provided for implementing an enhanced DRAM interface checking. An interface check mode enables interface checking using a refresh command for a DRAM. A predefined address pattern is provided for the interface address inputs during a refresh command cycle. Interface address inputs are checked for a proper value being applied and an error is signaled for unexpected results. An extended test mode includes further testing during a cycle after the refresh command cycle. Then command inputs also are checked for a proper value being applied and an error is signaled for unexpected results.

摘要翻译： 提供了一种用于实现增强的DRAM接口检查的方法，装置和计算机程序产品。 接口检查模式使用DRAM的刷新命令进行接口检查。 在刷新命令循环期间为接口地址输入提供预定义的地址模式。 检查接口地址输入是否正在应用值，并发出错误信号，以获取意外结果。 扩展测试模式包括在刷新命令周期之后的一个周期内的进一步测试。 然后，还将检查命令输入是否正在应用值，并发出错误信号，以获得意外结果。

公开(公告)号：US20060090112A1

公开(公告)日：2006-04-27

申请号：US10961745

申请日：2004-10-08

申请人： William Cochran ,  William Hovis ,  Paul Rudrud

发明人： William Cochran ,  William Hovis ,  Paul Rudrud

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F12/0804 ,  G06F12/084

摘要： Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.

公开(公告)号：US20080093683A1

公开(公告)日：2008-04-24

申请号：US11876379

申请日：2007-10-22

申请人： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

发明人： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

IPC分类号： H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L29/458 ,  H01L29/785

摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

摘要翻译： 公开了一种使用简化过程的改进的半导体互连方案的装置和方法。 在该装置的实施例中，在硅区域上形成多晶硅形状。 产生具有桥接顶点的多晶硅形状。 当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。 使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。

公开(公告)号：US20080029843A1

公开(公告)日：2008-02-07

申请号：US11873197

申请日：2007-10-16

申请人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

发明人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L29/41

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

摘要翻译： 一种电熔丝和一种用于制造集成多晶硅电阻掩模的电子熔丝的方法，以及设置有被检体E熔丝回路的设计结构。 电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。 硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。 非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。 非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

公开(公告)号：US20070210411A1

公开(公告)日：2007-09-13

申请号：US11372334

申请日：2006-03-09

申请人： William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

发明人： William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

IPC分类号： H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。

公开(公告)号：US20070202659A1

公开(公告)日：2007-08-30

申请号：US11696331

申请日：2007-04-04

申请人： Richard Donze ,  Karl Erickson ,  William Hovis ,  Terrance Kueper ,  John Sheets ,  Jon Tetzloff

发明人： Richard Donze ,  Karl Erickson ,  William Hovis ,  Terrance Kueper ,  John Sheets ,  Jon Tetzloff

IPC分类号： H01L21/76

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795

摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.

摘要翻译： 公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。 本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。 多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。 宽鳍片部分和多晶硅多边形形状的顶表面被硅化。 通过侧壁间隔物防止硅化物桥接。 多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。 中心区域与相关联的FinFET的源极和漏极相反地掺杂。

公开(公告)号：US20070168762A1

公开(公告)日：2007-07-19

申请号：US11290894

申请日：2005-11-30

申请人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

发明人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

IPC分类号： G06F11/00

CPC分类号： G06F11/1064 ,  G06F12/082

摘要： A method, and apparatus are provided for implementing a directory organization to selectively optimize performance or reliability in a computer system. A directory includes a user selected operational modes including a performance mode and a reliability mode. In the reliability mode, more directory bits are used for error correction and detection. In the performance mode, reclaimed directory bits not used for error correction and detection are used for more associativity.

摘要翻译： 提供了一种用于实现目录组织以选择性地优化计算机系统中的性能或可靠性的方法和装置。 目录包括用户选择的操作模式，包括演奏模式和可靠性模式。 在可靠性模式下，更多的目录位用于纠错和检测。 在性能模式下，不用于纠错和检测的回收目录位用于更多的关联性。

公开(公告)号：US20070083682A1

公开(公告)日：2007-04-12

申请号：US11246827

申请日：2005-10-07

申请人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

发明人： Gerald Bartley ,  John Borkenhagen ,  William Hovis ,  Daniel Kolz

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.

摘要翻译： 存储器控制器提供页面复制逻辑，以便在由存储器控制器复制页面期间在页面的DMA操作发生时确保数据一致性。 页面复制逻辑将DMA操作的页面索引与指示当前正在复制的位置的复制地址指针进行比较。 如果DMA操作的页面索引小于复制地址指针，则DMA操作将被写入的页面部分已被复制，因此DMA操作被执行到新页面的物理地址。 如果DMA操作的页面索引大于复制地址指针，则DMA操作将被写入的页面部分尚未被复制，因此DMA操作被执行到旧页面的物理地址 。