公开(公告)号：US20120212271A1

公开(公告)日：2012-08-23

申请号：US13033426

申请日：2011-02-23

申请人： William J. DALLY ,  Jonah M. Alben ,  John W. Poulton ,  GE (Francis) Yang

发明人： William J. DALLY ,  Jonah M. Alben ,  John W. Poulton ,  GE (Francis) Yang

IPC分类号： H03K3/02

CPC分类号： H03K3/36 ,  H03K3/012 ,  H03K3/356121

摘要： One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

摘要翻译： 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的双触发低能量触发器电路来捕获和存储输入信号电平的技术。 双触发低能触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。 时钟信号之一可以是低频“保持时钟”，其比输入到两个晶体管栅极的另外两个时钟信号频率更低。 输出信号Q在上升时钟沿使用分离的触发子电路设置或复位。 当时钟信号为低电平时，设置或复位可以布防，并且在时钟的上升沿触发置位或复位。

公开(公告)号：US20120320691A1

公开(公告)日：2012-12-20

申请号：US13159982

申请日：2011-06-14

申请人： William J. DALLY ,  John W. Poulton

发明人： William J. DALLY ,  John W. Poulton

IPC分类号： G11C7/12 ,  G11C7/10

CPC分类号： G11C11/412 ,  G11C7/12 ,  G11C11/419

摘要： One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the storage cell and a change in current on the bit line is converted by the clamping circuit to produce an amplified voltage that may be sampled to read a value stored in the storage cell. The clamping circuit maintains the nearly constant clamp voltage on the bit line. Clamping the bit line to the nearly constant clamp voltage reduces the occurrence of read disturb faults. Additionally, the clamping circuit functions with a variety of storage cells and does not require that the bit lines be precharged prior to each read operation.

摘要翻译： 本发明的一个实施例提出了一种钳位电路，其用于将存储单元的位线保持在几乎恒定的钳位电压。 在读取操作期间，位线被存储单元从钳位电压拉高或低电平，并且位线上的电流变化由钳位电路转换，以产生放大电压，该电压可被采样以读取存储在存储单元 存储单元。 钳位电路保持位线上几乎恒定的钳位电压。 将位线夹紧到几乎恒定的钳位电压可以减少读取干扰故障的发生。 此外，钳位电路具有各种存储单元的功能，并且不要求在每次读取操作之前对位线进行预充电。

公开(公告)号：US20120206182A1

公开(公告)日：2012-08-16

申请号：US13028023

申请日：2011-02-15

申请人： William J. DALLY

发明人： William J. DALLY

IPC分类号： H03K3/00

CPC分类号： H03K3/356191 ,  H03K3/012

摘要： One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a low-clock-energy latch circuit that is fully static. The clock is only coupled to a first clock-activated pull-up or pull-down transistor and a second clock-activated pull-down or pull-up transistor. The level of the input signal is captured by a storage sub-circuit on one of the rising or the falling clock edge and stored to generate an output signal until the clock transitions. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled and disabled by the first clock-activated transistor and a propagation sub-circuit is activated and deactivated by the second clock-activated transistor.

摘要翻译： 本发明的一个实施例提出了一种使用完全静态的低时钟能量锁存电路捕获和保持输入信号电平的技术。 时钟仅耦合到第一个时钟激活的上拉或下拉晶体管和第二个时钟激活的下拉或上拉晶体管。 输入信号的电平由存储子电路在上升沿或下降沿之一被捕获，并被存储以产生输出信号直到时钟转变。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由第一时钟激活晶体管使能和禁止，并且传播子电路被第二时钟激活晶体管激活和去激活。