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    DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT
    2.
    发明申请
    DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT 有权
    双触发低能量FLIP-FLOP电路

    公开(公告)号：US20120212271A1

    公开(公告)日：2012-08-23

    申请号：US13033426

    申请日：2011-02-23

    申请人： William J. DALLY ,  Jonah M. Alben ,  John W. Poulton ,  GE (Francis) Yang

    发明人： William J. DALLY ,  Jonah M. Alben ,  John W. Poulton ,  GE (Francis) Yang

    IPC分类号： H03K3/02

    CPC分类号： H03K3/36 ,  H03K3/012 ,  H03K3/356121

    摘要： One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

    摘要翻译： 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的双触发低能量触发器电路来捕获和存储输入信号电平的技术。 双触发低能触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。 时钟信号之一可以是低频“保持时钟”，其比输入到两个晶体管栅极的另外两个时钟信号频率更低。 输出信号Q在上升时钟沿使用分离的触发子电路设置或复位。 当时钟信号为低电平时，设置或复位可以布防，并且在时钟的上升沿触发置位或复位。

    Real-time display post-processing using programmable hardware
    4.
    发明授权
    Real-time display post-processing using programmable hardware 有权
    使用可编程硬件实时显示后处理

    公开(公告)号：US07586492B2

    公开(公告)日：2009-09-08

    申请号：US11019414

    申请日：2004-12-20

    申请人： Duncan A. Riach ,  John M. Danskin ,  Jonah M. Alben ,  Michael A. Ogrinc ,  Anthony Michael Tamasi

    发明人： Duncan A. Riach ,  John M. Danskin ,  Jonah M. Alben ,  Michael A. Ogrinc ,  Anthony Michael Tamasi

    IPC分类号： G06F15/16 ,  G06F9/46 ,  G09G5/399

    CPC分类号： G09G5/363 ,  G06F3/1431 ,  G06T15/005 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G09G2310/04 ,  G09G2360/125 ,  G09G2360/127

    摘要： In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.

    摘要翻译： 在图形处理器中，渲染对象和后处理对象与可编程执行核共享对主处理器的访问。 渲染对象从几何数据生成图像的碎片数据。 后处理对象操作以从片段数据生成像素数据帧，并将像素数据存储在帧缓冲器中。 与主处理器的操作并行，扫描引擎引擎读取先前产生的帧的像素数据，并将像素数据提供给显示设备。 扫描引擎周期性地触发主处理器来操作后处理对象以产生下一帧。 可以控制扫描输出引擎和后处理对象之间的时序，使得当扫描引擎引擎完成读取当前帧时，待显示的下一帧准备在帧缓冲器中。

    Surrogate stencil buffer clearing
    5.
    发明授权
    Surrogate stencil buffer clearing 有权
    代理模板缓冲液清理

    公开(公告)号：US07355602B1

    公开(公告)日：2008-04-08

    申请号：US10985699

    申请日：2004-11-10

    申请人： Mark J. Kilgard ,  Jonah M. Alben ,  Cass W. Everitt

    发明人： Mark J. Kilgard ,  Jonah M. Alben ,  Cass W. Everitt

    IPC分类号： G09G5/36

    CPC分类号： G06T11/40

    摘要： Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil buffer since the last actual clear. Bits are reserved in each stencil register for storing the surrogate clear number that cleared other stencil registers the last time the stencil register held an assigned value. A comparison between the contents of the hardware register and the reserved bits in each stencil register determines if each stencil register should be assigned a cleared value. If the numbers do not match the stencil register is assigned a predetermined surrogate clear value. In some applications the number of reserved bits is fixed, while in other applications the number of reserved bits can be set, either by a designer or by software.

    摘要翻译： 使用代理模板缓冲液清除高效清除模板缓冲器的方法和装置。 硬件寄存器跟踪自上次实际清除以来模板缓冲区的代理清除次数。 每个模板寄存器保留位，用于存储上一次模板寄存器保持分配值时清除其他模板寄存器的代理清除号。 硬件寄存器的内容和每个模板寄存器中的保留位之间的比较确定每个模板寄存器是否应被分配一个清零的值。 如果数字不匹配，模板寄存器将分配一个预定的代理清除值。 在某些应用中，保留位的数量是固定的，而在其他应用中，可以由设计者或软件来设置保留位数。

    Memory clock slowdown synthesis circuit
    6.
    发明授权
    Memory clock slowdown synthesis circuit 有权
    内存时钟减速合成电路

    公开(公告)号：US07042263B1

    公开(公告)日：2006-05-09

    申请号：US10742572

    申请日：2003-12-18

    申请人： Philip Browning Johnson ,  Jonah M. Alben ,  Sean Jeffrey Treichler ,  Adam E. Levinthal

    发明人： Philip Browning Johnson ,  Jonah M. Alben ,  Sean Jeffrey Treichler ,  Adam E. Levinthal

    IPC分类号： H03K3/356

    CPC分类号： G06F1/325 ,  G06F1/08 ,  G06F1/12 ,  G06F1/3215

    摘要： Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.

    摘要翻译： 通过产生两个存储器时钟信号来减少图形处理器集成电路上的功率的电路，方法和装置，在一定条件下降低一个频率，并保持另一个的频率。 为了减少这两个存储器时钟之间的偏移和抖动，并且为了确保它们保持同相，本发明的示例性实施例使用同步器电路。 同步器电路也可用作通用应用时钟发生器。

    System for programmable dithering of video data
    7.
    发明授权
    System for programmable dithering of video data 有权

    公开(公告)号：US06982722B1

    公开(公告)日：2006-01-03

    申请号：US10233657

    申请日：2002-09-03

    申请人： Jonah M. Alben ,  Stephen Lew

    发明人： Jonah M. Alben ,  Stephen Lew

    IPC分类号： G09G5/02

    CPC分类号： G09G3/2048 ,  G09G5/02 ,  G09G5/363 ,  G09G2320/0247

    摘要： A programmable system for dithering video data. The system is operable in at least two user-selectable modes which can include a small kernel mode and a large kernel mode. In some embodiments, the system is operable in at least one mode in which it applies two or more kernels (each from a different kernel sequence) to each block of video words. Each kernel sequence repeats after a programmable number of the blocks (e.g., a programmable number of frames containing the blocks) have been dithered. The period of repetition is preferably programmable independently for each kernel sequence. The system preferably includes a frame counter for each kernel sequence. Each counter generates an interrupt when the number of frames of data dithered by kernels of the sequence has reached a predetermined value. In response to the interrupt, software can change the kernel sequence being applied. Typically, the system performs both truncation and dithering on words of video data. For example, some embodiments produce dithered 6-bit color components in response to 8-bit input color component words. Preferably, the inventive system is optionally operable in either a normal mode (in which dithering is applied to all pixels in accordance with the invention) or in an anti-flicker mode. Another aspect of the invention is a computer system in which the dithering system is implemented as a subsystem of a pipelined graphics processor or display device. Another aspect of the invention is a display device that includes an embodiment of the dithering system.

    System and method for avoiding depth clears using a stencil buffer
    8.
    发明授权
    System and method for avoiding depth clears using a stencil buffer 有权
    使用模板缓冲区避免深度清除的系统和方法

    公开(公告)号：US06812927B1

    公开(公告)日：2004-11-02

    申请号：US10175199

    申请日：2002-06-18

    申请人： Scott P. Cutler ,  Jonah M. Alben

    发明人： Scott P. Cutler ,  Jonah M. Alben

    IPC分类号： G06T120

    CPC分类号： G06T1/20

    摘要： A system and method are provided for reducing the number of depth clear operations in a hardware graphics pipeline. Initially, a frame count is stored into a frame buffer associated with the hardware graphics pipeline. The stored frame count is associated with a pixel. A depth clear operation is then performed based at least in part on the frame count utilizing the hardware graphics pipeline.

    摘要翻译： 提供了一种用于减少硬件图形管线中的深度清除操作的数量的系统和方法。 最初，将帧计数存储到与硬件图形流水线相关联的帧缓冲器中。 存储的帧计数与像素相关联。 然后至少部分地基于使用硬件图形管线的帧计数来执行深度清晰操作。

    System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message
    9.
    发明授权
    System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message 有权
    使用窥探请求和完整消息在串行接口总线上维护高速缓存一致性的系统和方法

    公开(公告)号：US08782349B2

    公开(公告)日：2014-07-15

    申请号：US13557980

    申请日：2012-07-25

    申请人： Brian Keith Langendorf ,  David B. Glasco ,  Michael Brian Cox ,  Jonah M. Alben

    发明人： Brian Keith Langendorf ,  David B. Glasco ,  Michael Brian Cox ,  Jonah M. Alben

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0831

    摘要： Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus and causing the snoop request to be transmitted over the serial interface bus to a second processor. The techniques further include extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.

    摘要翻译： 公开了用于通过串行接口总线（例如外围组件互连Express（PCIe）总线）来维持高速缓存一致性的技术。 这些技术包括产生窥探请求（SNP）以确定存储在本地存储器中的第一数据是否相对于存储在数据高速缓存中的第二数据是相干的，该窥探请求包括识别串行接口总线上的数据高速缓存的目的地信息，并导致 通过串行接口总线传送到第二处理器的窥探请求。 所述技术还包括从窥探请求中提取高速缓存线地址，确定第二数据是否相干，生成指示第一数据与第二数据相干的完整消息（CPL），并且使得完整的消息被传送 总线到第一个处理器。 窥探请求和完成消息可以是供应商定义的消息。

    Memory clock slowdown
    10.
    发明授权
    Memory clock slowdown 有权
    内存时钟减速

    公开(公告)号：US08707081B2

    公开(公告)日：2014-04-22

    申请号：US12902147

    申请日：2010-10-12

    申请人： Jonah M. Alben ,  Sean Jeffrey Treichler ,  Adam E. Levinthal

    发明人： Jonah M. Alben ,  Sean Jeffrey Treichler ,  Adam E. Levinthal

    IPC分类号： G06F1/32

    CPC分类号： H03L7/06

    摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.

    摘要翻译： 用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。 本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。 切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。 在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。 本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。