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公开(公告)号：US08949520B2
公开(公告)日：2015-02-03
申请号：US13145542
申请日：2010-01-13
CPC分类号： G06F3/0619 , G06F3/0629 , G06F3/0659 , G06F3/0673 , G06F13/1636 , G06F13/1689 , G06Q10/00 , G06Q20/00 , G11C7/02 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C2211/4061
摘要： A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
摘要翻译： 一种系统包括存储器控制器和具有命令接口和多个存储器组的存储器件，每个存储体具有多行存储器单元。 存储器控制器向存储器件发送自动刷新命令。 响应于自动刷新命令，在第一时间间隔期间，存储器件执行刷新操作以刷新存储器单元，并且存储器件的命令接口在第一时间间隔的持续时间内被置于校准模式。 同时，在第一时间间隔的至少一部分期间，存储器控制器执行存储器件的命令接口的校准。 自动刷新命令可以指定要刷新存储器件的存储体的顺序，使得存储器件以指定的存储体顺序顺序地刷新多个存储体中的相应行。
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2.发明授权Configurable, power supply voltage referenced single-ended signaling with ESD protection 有权可配置的电源电压参考具有ESD保护的单端信号公开(公告)号：US08605397B2
公开(公告)日：2013-12-10
申请号：US13318475
申请日：2010-03-29
IPC分类号： H02H3/22
CPC分类号： H04B3/56 , G06F13/4072 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2924/15311 , H03F3/24 , H04B3/54 , H04B10/0731 , H04B10/40 , H04B10/50 , H04B2001/0408 , H04L25/0272 , H01L2924/00014
摘要： A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
摘要翻译： 单端数据传输系统传输具有参考电源电压并且在电源电压之上和之下摆动的信号电压的信号。 电源电压耦合到也用作信号返回路径的电源轨。 信号电压是由一对电荷泵产生的两个信号电源电压得出的，该电荷泵从电源中抽取大致相同的电流量。
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公开(公告)号：US08559248B2
公开(公告)日：2013-10-15
申请号：US13159982
申请日：2011-06-14
申请人： William J. Dally , John W. Poulton
发明人： William J. Dally , John W. Poulton
IPC分类号： G11C16/04
CPC分类号： G11C11/412 , G11C7/12 , G11C11/419
摘要： One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the storage cell and a change in current on the bit line is converted by the clamping circuit to produce an amplified voltage that may be sampled to read a value stored in the storage cell. The clamping circuit maintains the nearly constant clamp voltage on the bit line. Clamping the bit line to the nearly constant clamp voltage reduces the occurrence of read disturb faults. Additionally, the clamping circuit functions with a variety of storage cells and does not require that the bit lines be precharged prior to each read operation.
摘要翻译： 本发明的一个实施例提出了一种钳位电路，其用于将存储单元的位线保持在几乎恒定的钳位电压。 在读取操作期间，位线被存储单元从钳位电压拉高或低电平，并且位线上的电流变化由钳位电路转换，以产生放大电压，该电压可被采样以读取存储在存储单元 存储单元。 钳位电路保持位线上几乎恒定的钳位电压。 将位线夹紧到几乎恒定的钳位电压可以减少读取干扰故障的发生。 此外，钳位电路具有各种存储单元的功能，并且不要求在每次读取操作之前对位线进行预充电。
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公开(公告)号：US08509094B2
公开(公告)日：2013-08-13
申请号：US12745489
申请日：2008-12-02
申请人： Andrew M. Fuller , John W. Poulton
发明人： Andrew M. Fuller , John W. Poulton
IPC分类号： G01R31/08
CPC分类号： H04L25/0262 , H04L1/20 , H04L1/246
摘要： Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data.
摘要翻译： 为基于边缘的信号丢失（LOS）检测提供了系统和方法。 在接收机中，接收端口接收数据信号。 耦合到接收端口的时钟和数据恢复（CDR）机制导出一个或多个时钟信号。 LOS信号产生机制基于接收端口不接收可用数据时出现的边缘毛刺产生LOS信号。
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公开(公告)号：US20120176156A1
公开(公告)日：2012-07-12
申请号：US13497340
申请日：2010-09-16
IPC分类号： H03K19/0175 , H03K5/153
CPC分类号： H04L25/0278
摘要： A single-ended signaling system in which transmitted and returned signal currents are enabled to flow substantially parallel to one another and thereby maintain a substantially uniform impedance along the length of a single-ended signal conductor. A reference plane is disposed substantially parallel to a single-ended signaling conductor and coupled to the signaling conductor within a signal-receiving IC and to signaling supply voltage nodes within a signal-transmitting IC. By this arrangement, an signal current flowing to or from the receiving IC via the signaling conductor is conducted to the reference plane, thereby enabling a signal-return current to flow back to or back from the transmitting IC along a single path that is substantially parallel to the signal conductor.
摘要翻译： 一种单端信号系统，其中传输和返回的信号电流能够基本上彼此平行地流动，从而沿着单端信号导体的长度保持基本均匀的阻抗。 基准平面布置成基本上平行于单端信令导体，并且耦合到信号接收IC内的信号导体，并且信号传送IC内的电源电压节点。 通过这种布置，经由信号导体流向或从接收IC流出的信号电流被传导到参考平面，从而使得信号返回电流沿着基本上平行的单个路径从发送IC流回或返回 到信号导体。
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公开(公告)号：US20120147979A1
公开(公告)日：2012-06-14
申请号：US13391223
申请日：2010-03-30
申请人： Scott C. Best , John W. Poulton
发明人： Scott C. Best , John W. Poulton
IPC分类号： H04L27/00
CPC分类号： G11C5/144 , G06F11/0727 , G06F11/076 , G06F11/0793 , G06F13/4072 , G11C5/145 , H04L1/203 , H04L25/0264 , H04L25/08
摘要： In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
摘要翻译： 在数据传输系统中，在第一电路中生成用于产生要发送的信号的信令电压的一个或多个信号电源电压，并从第一电路转发到第二电路。 第二电路可以使用转发的信号电源电压来产生要从第二电路传输回第一电路的另一个信号，从而避免在第二电路中单独产生信号电源电压的需要。 第一电路还可以基于从第二电路传输回第一电路的信号来调整信号电源电压。 数据传输系统可以使用单端信令系统，其中信令电压参考作为由第一电路和第二电路共享的诸如地的电源电压的参考电压。
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7.发明申请公开(公告)号：US20120044984A1
公开(公告)日：2012-02-23
申请号：US13284002
申请日：2011-10-28
申请人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian Leibowitz
发明人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian Leibowitz
IPC分类号： H04L27/01
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
摘要翻译： 一个信令系统包括一个预先强调的发射机和一个通过高速信号路径相互耦合的均衡接收机。 接收机测量从发射机传送的数据的质量。 控制器使用该信息和其他信息来自适应地建立适当的发送预加重和接收均衡设置，例如， 选择信令系统提供一些最小通信带宽而不超过所需误码率的最低功率设置。
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公开(公告)号：US20110283060A1
公开(公告)日：2011-11-17
申请号：US13145542
申请日：2010-01-13
IPC分类号： G06F12/00
CPC分类号： G06F3/0619 , G06F3/0629 , G06F3/0659 , G06F3/0673 , G06F13/1636 , G06F13/1689 , G06Q10/00 , G06Q20/00 , G11C7/02 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C2211/4061
摘要： A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
摘要翻译： 一种系统包括存储器控制器和具有命令接口和多个存储器组的存储器件，每个存储体具有多行存储器单元。 存储器控制器向存储器件发送自动刷新命令。 响应于自动刷新命令，在第一时间间隔期间，存储器件执行刷新操作以刷新存储器单元，并且存储器件的命令接口在第一时间间隔的持续时间内被置于校准模式。 同时，在第一时间间隔的至少一部分期间，存储器控制器执行存储器件的命令接口的校准。 自动刷新命令可以指定要刷新存储器件的存储体的顺序，使得存储器件以指定的存储体顺序顺序地刷新多个存储体中的相应行。
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9.发明申请公开(公告)号：US20110239031A1
公开(公告)日：2011-09-29
申请号：US13132094
申请日：2009-07-09
IPC分类号： G06F1/00
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译： 在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。 开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。 每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。
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公开(公告)号：US20100085100A1
公开(公告)日：2010-04-08
申请号：US12525181
申请日：2008-02-12
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.
摘要翻译： 通信IC包括功率高效的时钟分配系统。 控制回路监视和调整时钟信号的峰值和谷底电压。 可以自适应地调整时钟信号以使峰值和谷值电压围绕时钟缓冲器的开关阈值电压。 因此，可以使时钟信号的电压摆幅变小，结果是功率有效。 控制回路可以监视和控制多个时钟信号。
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