-
公开(公告)号：US08268698B2
公开(公告)日：2012-09-18
申请号：US13037608
申请日：2011-03-01
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译： 本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。 每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。 垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。 气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。
-
公开(公告)号：US20090039461A1
公开(公告)日：2009-02-12
申请号：US12254197
申请日：2008-10-20
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译： 本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。 每个器件区域至少包括基底半导体衬底层和位于它们之间的掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。 垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。 气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。
-
公开(公告)号：US20070275537A1
公开(公告)日：2007-11-29
申请号：US11420279
申请日：2006-05-25
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译： 本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。 每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。 垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。 气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。
-
公开(公告)号：US07932158B2
公开(公告)日：2011-04-26
申请号：US12254197
申请日：2008-10-20
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译： 本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。 每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。 垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，该半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。 气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。
-
公开(公告)号：US20110147885A1
公开(公告)日：2011-06-23
申请号：US13037608
申请日：2011-03-01
IPC分类号： H01L23/58
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译： 本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。 每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。 垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。 气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。
-
公开(公告)号：US07452784B2
公开(公告)日：2008-11-18
申请号：US11420279
申请日：2006-05-25
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译： 本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。 每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。 垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。 气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。
-
7.发明授权Stress engineering using dual pad nitride with selective SOI device architecture 有权使用双衬垫氮化物的应力工程与选择性SOI器件架构公开(公告)号：US07202513B1
公开(公告)日：2007-04-10
申请号：US11162953
申请日：2005-09-29
IPC分类号： H01L31/00
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0653 , H01L29/7842
摘要： A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.
摘要翻译： 描述了一种使用高应力氮化物膜与选择性绝缘体上半导体（SOI）器件结构结合的在不同导电性的MOS晶体管的沟道中应力的方法。 描述了在浅沟槽隔离（STI）工艺中使用压缩和拉伸氮化物膜的方法。 当将该方法应用于选择性SOI结构时，实现高应力值。
-
公开(公告)号：US20100013024A1
公开(公告)日：2010-01-21
申请号：US12506770
申请日：2009-07-21
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译： 本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。 在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。
-
公开(公告)号：US07615418B2
公开(公告)日：2009-11-10
申请号：US11380688
申请日：2006-04-28
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
摘要翻译： 一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。
-
公开(公告)号：US07791144B2
公开(公告)日：2010-09-07
申请号：US12506770
申请日：2009-07-21
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译： 本发明涉及一种制造半导体结构和方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极中的应力诱导材料以及PFET和NFET沟道的变化的厚度。 在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。
-
-
-
-
-
-
-
-
-
搜索结果
99 条记录 (耗时 0.031 秒)
