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    Non-volatile semiconductor memory device and erasing method thereof
    3.
    发明授权
    Non-volatile semiconductor memory device and erasing method thereof 有权

    公开(公告)号：US09786376B2

    公开(公告)日：2017-10-10

    申请号：US15140509

    申请日：2016-04-28

    申请人： Winbond Electronics Corp.

    发明人： Pin-Yao Wang

    IPC分类号： G11C16/16 ,  G11C16/04 ,  G11C16/32

    CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/32

    摘要： A non-volatile semiconductor memory device achieving low power consumption and erasing method thereof is provided. The flash memory of the present invention includes a memory array formed with NAND type strings. The memory array includes a plurality of global blocks, one global block includes a plurality of blocks, and one block includes a plurality of NAND type strings. When the block of the selected global block is erased and the next block is in adjacent relationship, electric charge accumulated in one of P-wells is discharged to another one of the P-wells, and then the next selected block is erased. Thus, the electric charge is shared between the adjacent P-wells to achieve low power consumption.

    Semiconductor device, method of manufacturing the same and generation method of unique information
    4.
    发明授权
    Semiconductor device, method of manufacturing the same and generation method of unique information 有权

    公开(公告)号：US10242950B2

    公开(公告)日：2019-03-26

    申请号：US15631889

    申请日：2017-06-23

    申请人： Winbond Electronics Corp.

    发明人： Masaru Yano ,  Pin-Yao Wang

    IPC分类号： G06F17/50 ,  G06F19/00 ,  H01L23/00 ,  H01L23/544 ,  G05B19/12 ,  G11C16/22 ,  H01L21/66

    摘要： A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or fabricated based on a general design condition or manufacturing condition, an input/output circuit, and a unique-information generation circuit to generate unique information of the semiconductor device. The unique-information generation circuit includes a circuit for PUF and a code-generation unit. The circuit for PUF is fabricated based on the design condition or manufacturing condition which is different from the general design condition or manufacturing condition and has a factor which makes variations of circuit components become large. The code-generation unit generates codes based on the output of the circuit for PUF.

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ERASING METHOD THEREOF
    6.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ERASING METHOD THEREOF 有权

    公开(公告)号：US20170133094A1

    公开(公告)日：2017-05-11

    申请号：US15140509

    申请日：2016-04-28

    申请人： Winbond Electronics Corp.

    发明人： Pin-Yao Wang

    IPC分类号： G11C16/16 ,  G11C16/04

    CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/32

    摘要： A non-volatile semiconductor memory device achieving low power consumption and erasing method thereof is provided. The flash memory of the present invention includes a memory array formed with NAND type strings. The memory array includes a plurality of global blocks, one global block includes a plurality of blocks, and one block includes a plurality of NAND type strings. When the block of the selected global block is erased and the next block is in adjacent relationship, electric charge accumulated in one of P-wells is discharged to another one of the P-wells, and then the next selected block is erased. Thus, the electric charge is shared between the adjacent P-wells to achieve low power consumption.

    MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件的制造方法

    公开(公告)号：US20160358929A1

    公开(公告)日：2016-12-08

    申请号：US15237640

    申请日：2016-08-16

    申请人： Winbond Electronics Corp.

    发明人： Masaru Yano ,  Pin-Yao Wang

    IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308

    CPC分类号： H01L27/11524 ,  G11C8/14 ,  G11C16/12 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/66553 ,  H01L29/66825

    摘要： A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

    摘要翻译： 提供一种半导体存储器件的制造方法。 半导体存储器件可以抑制在编程动作期间产生的电流泄漏，从而可以以高可靠性执行编程动作。 本发明的闪存具有形成NAND型串的存储器阵列。 字符串行方向上的存储单元的门通常连接到字线。 位线选择晶体管的栅极通常连接到选择栅极线（SGD）。 源极线选择晶体管的栅极通常连接到选择栅极线（SGS）。 选择栅极线（SGS）的间隔（S4）和与选择栅极线（SGS）相邻的字线（WL0）的栅极大于选择栅极线（SGD）的间隔（S1），并且a 与选择栅线（SGD）相邻的字线（WL7）的栅极。

    Semiconductor memory device and manufacturing method thereof
    8.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09449697B2

    公开(公告)日：2016-09-20

    申请号：US14621344

    申请日：2015-02-12

    申请人： Winbond Electronics Corp.

    发明人： Masaru Yano ,  Pin-Yao Wang

    IPC分类号： G11C11/34 ,  G11C16/12 ,  H01L27/115 ,  G11C8/14

    CPC分类号： H01L27/11524 ,  G11C8/14 ,  G11C16/12 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/66553 ,  H01L29/66825

    摘要： A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

    摘要翻译： 提供一种半导体存储器件，其可以抑制在编程动作期间产生的电流泄漏，使得可以以高可靠性执行编程动作。 本发明的闪存具有形成NAND型串的存储器阵列。 字符串行方向上的存储单元的门通常连接到字线。 位线选择晶体管的栅极通常连接到选择栅极线（SGD）。 源极线选择晶体管的栅极通常连接到选择栅极线（SGS）。 选择栅极线（SGS）的间隔（S4）和与选择栅极线（SGS）相邻的字线（WL0）的栅极大于选择栅极线（SGD）的间隔（S1），并且a 与选择栅线（SGD）相邻的字线（WL7）的栅极。

    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20150380092A1

    公开(公告)日：2015-12-31

    申请号：US14621344

    申请日：2015-02-12

    申请人： Winbond Electronics Corp.

    发明人： Masaru Yano ,  Pin-Yao Wang

    IPC分类号： G11C16/12 ,  H01L27/115 ,  H01L21/28

    CPC分类号： H01L27/11524 ,  G11C8/14 ,  G11C16/12 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/66553 ,  H01L29/66825

    摘要： A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

    摘要翻译： 提供一种半导体存储器件，其可以抑制在编程动作期间产生的电流泄漏，从而可以以高可靠性执行编程动作。 本发明的闪存具有形成NAND型串的存储器阵列。 字符串行方向上的存储单元的门通常连接到字线。 位线选择晶体管的栅极通常连接到选择栅极线（SGD）。 源极线选择晶体管的栅极通常连接到选择栅极线（SGS）。 选择栅极线（SGS）的间隔（S4）和与选择栅极线（SGS）相邻的字线（WL0）的栅极大于选择栅极线（SGD）的间隔（S1），并且a 与选择栅线（SGD）相邻的字线（WL7）的栅极。