公开(公告)号：US12080353B2

公开(公告)日：2024-09-03

申请号：US17988782

申请日：2022-11-17

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Toshiaki Takeshita

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/3445

Abstract: The disclosure provides a semiconductor device and an erasing method that may alleviate the deterioration of a memory cell caused by ISPE. The NAND flash memory in the disclosure includes a memory cell array and an erasing component that erases selected blocks of the memory cell array. The erasing component performs a first erasing verification (EV1) and a second erasing verification (EV2) on the selected block. When the first erasing verification (EV1) passes, and the second erasing verification (EV2) fails, an erase pulse with the same erase voltage as the last time is applied, and when the first erasing verification (EV1) fails, an erase pulse with a step voltage higher than the last time is applied.

公开(公告)号：US11798628B2

公开(公告)日：2023-10-24

申请号：US17462006

申请日：2021-08-31

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Toshiaki Takeshita

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/349 ,  G11C16/3459

Abstract: A semiconductor storage apparatus programming a memory cell through improved ISPP is introduced. A NAND flash memory programming method includes a step of selecting a page of a memory cell array and applying a programming pulse based on the ISPP to the selected page. The programming pulse applied by the ISPP includes a sacrificial programming pulse for which a program verification becomes unqualified due to an initial programming pulse and a last programming pulse having an increment larger than any increment of other programming pulses.

公开(公告)号：US09627963B2

公开(公告)日：2017-04-18

申请号：US15012424

申请日：2016-02-01

Applicant: WINBOND ELECTRONICS CORP.

Inventor： Toshiaki Takeshita

IPC: G11C16/10 ,  H02M3/07 ,  G11C16/30 ,  G11C5/14

CPC classification number: H02M3/07 ,  G11C5/145 ,  G11C5/147 ,  G11C16/30 ,  H02M3/073

Abstract: A voltage generation circuit is provided to suppress the required layout of the voltage generation circuit and stabilize the output voltage thereof.[Solution]A voltage generation circuit 100A according to the present invention includes a charge pump circuit 20, a resistor voltage-division circuit 120, a comparator 34 having a voltage Vm output from the resistor voltage-division circuit 120 and a reference voltage, and a control circuit 36 controlling the operation of the charge pump circuit 20 based on the comparison result of the comparator 34. The resistor voltage-division circuit 120 includes resistors R1˜R4 connected in series between an output node NOUT and a ground and generates the voltage Vm at a voltage-division node NR in response to an output voltage VOUT. The resistor voltage-division circuit 120 further includes a parasitic capacitor Cp to capacitively couple the resistors R1, R2, R3 and R4 to the output node NOUT.

公开(公告)号：US20230186997A1

公开(公告)日：2023-06-15

申请号：US17988782

申请日：2022-11-17

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Toshiaki Takeshita

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/3445

Abstract: The disclosure provides a semiconductor device and an erasing method that may alleviate the deterioration of a memory cell caused by ISPE. The NAND flash memory in the disclosure includes a memory cell array and an erasing component that erases selected blocks of the memory cell array. The erasing component performs a first erasing verification (EV1) and a second erasing verification (EV2) on the selected block. When the first erasing verification (EV1) passes, and the second erasing verification (EV2) fails, an erase pulse with the same erase voltage as the last time is applied, and when the first erasing verification (EV1) fails, an erase pulse with a step voltage higher than the last time is applied.

公开(公告)号：US20220068393A1

公开(公告)日：2022-03-03

申请号：US17462006

申请日：2021-08-31

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Toshiaki Takeshita

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: A semiconductor storage apparatus programming a memory cell through improved ISPP is introduced. A NAND flash memory programming method includes a step of selecting a page of a memory cell array and applying a programming pulse based on the ISPP to the selected page. The programming pulse applied by the ISPP includes a sacrificial programming pulse for which a program verification becomes unqualified due to an initial programming pulse and a last programming pulse having an increment larger than any increment of other programming pulses.