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    MEMORY DEVICE WITH SECURE TEST MODE
    2.
    发明申请
    MEMORY DEVICE WITH SECURE TEST MODE 有权
    具有安全测试模式的存储器件

    公开(公告)号：US20150287477A1

    公开(公告)日：2015-10-08

    申请号：US14244000

    申请日：2014-04-03

    申请人： Winbond Electronics Corporation

    发明人： Nir Tasher ,  Uri Kaluzhny ,  Tsachi Weiser ,  Valery Teper

    IPC分类号： G11C29/38 ,  G06F21/79

    CPC分类号： G06F11/0769 ,  G06F11/073 ,  G06F11/26 ,  G06F21/79 ,  G11C7/24 ,  G11C29/12 ,  G11C29/38

    摘要： A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.

    摘要翻译： 一种在测试模式下操作的存储器件中的方法，包括接收要写入存储器件的向量。 只有当向量属于预定义的一组测试向量时，才将向量写入存储器件。 如果矢量不属于一组测试矢量，则将矢量转换为一个测试矢量，并将转换的矢量写入存储器件。

    State-machine clock tampering detection
    3.
    发明授权
    State-machine clock tampering detection 有权
    状态机时钟篡改检测

    公开(公告)号：US09223960B1

    公开(公告)日：2015-12-29

    申请号：US14447644

    申请日：2014-07-31

    申请人： WINBOND ELECTRONICS CORPORATION

    发明人： Uri Kaluzhny ,  Tsachi Weiser ,  Valery Teper ,  Nir Tasher

    IPC分类号： G06F21/50 ,  G06F11/07

    CPC分类号： G06F11/1604 ,  G06F1/04 ,  G06F21/725

    摘要： An apparatus for detecting tampering with a clock of a state-machine, comprising, a master state-machine having master states and driven by a master clock, the master states being switchable responsive to events, and an auxiliary state-machine having auxiliary states and driven by an auxiliary clock synchronous with the master clock, the auxiliary states being switchable responsive to a signal generated based at least on said events, consequently establishing a correspondence between the master states and the auxiliary states, thus ensuing that subsequent to tampering with the master clock the correspondence between the master states and the auxiliary states become discordant, thereby indicating that the master clock has been tampered with.

    摘要翻译： 一种用于检测篡改状态机的时钟的装置，包括具有主状态并由主时钟驱动的主状态机，主状态可响应于事件而切换，以及辅助状态机具有辅助状态和 由与主时钟同步的辅助时钟驱动，辅助状态可响应于至少基于所述事件产生的信号进行切换，从而建立主状态和辅助状态之间的对应关系，从而随后篡改主机 时钟，主状态和辅助状态之间的对应关系变得不一致，从而表明主时钟已被篡改。