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    METHOD FOR REDUCING INTERFERENCE IN A RADIO COMMUNICATION SYSTEM
    1.
    发明申请
    METHOD FOR REDUCING INTERFERENCE IN A RADIO COMMUNICATION SYSTEM 审中-公开
    用于减少无线电通信系统干扰的方法

    公开(公告)号：US20080125154A1

    公开(公告)日：2008-05-29

    申请号：US11943669

    申请日：2007-11-21

    申请人： Wolfgang ZIRWAS ,  Haifeng CHEN ,  Volker JUNGNICKEL ,  Volker POHL ,  Tobias WEBER

    发明人： Wolfgang ZIRWAS ,  Haifeng CHEN ,  Volker JUNGNICKEL ,  Volker POHL ,  Tobias WEBER

    IPC分类号： H04B7/00 ,  H04K1/10

    CPC分类号： H04B7/022 ,  H04B7/0837

    摘要： According to the invention, a method for reducing interference in a radio communication system is proposed, wherein a user terminal is equipped with at least two antennas for receiving at least two signal streams using a space-time processing technique, wherein the at least two signal streams are received from at least two transmit antennas of at least two base stations, and wherein the at least two signal streams are distinguished by orthogonal sequences.

    摘要翻译： 根据本发明，提出了一种用于减少无线电通信系统中的干扰的方法，其中用户终端配备有至少两个天线，用于使用时空处理技术来接收至少两个信号流，其中所述至少两个信号 从至少两个基站的至少两个发射天线接收流，并且其中所述至少两个信号流由正交序列区分。

    HARDWARE ACCELERATOR MODULE AND METHOD FOR SETTING UP SAME
    2.
    发明申请
    HARDWARE ACCELERATOR MODULE AND METHOD FOR SETTING UP SAME 失效
    硬件加速器模块及其设置方法

    公开(公告)号：US20120084543A1

    公开(公告)日：2012-04-05

    申请号：US13251323

    申请日：2011-10-03

    申请人： Uwe PROSS ,  Tobias WEBER ,  Gunnar NITSCHE ,  Thomas FLIESS

    发明人： Uwe PROSS ,  Tobias WEBER ,  Gunnar NITSCHE ,  Thomas FLIESS

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3881

    摘要： A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.

    摘要翻译： 硬件加速器模块由系统处理器经由系统总线驱动，以便根据由处理器定义的参数集来顺序地处理数据流的数据块。 模块包括适于从系统处理器接收参数集的寄存器块，适于接收流数据的加速器核心，以由参数集定义的方式处理所述流数据的数据块，以及输出处理后的流数据，以及 参数缓冲块，其适于连续地存储多个参数集，并且作为硬件加速器核心的忙状态的函数，将参数集顺序地提供给硬件加速器核心。 参数缓冲块可以减少硬件加速器的停机时间，增加数据吞吐量，并降低驱动多个硬件加速器的处理器中处理器过载的风险。