公开(公告)号：US20110241099A1

公开(公告)日：2011-10-06

申请号：US13038117

申请日：2011-03-01

申请人： Woo-Song Ahn ,  Satoru Yamada ,  Young-Jin Choi ,  Seung-Uk Han ,  Kyo-Suk Chae

发明人： Woo-Song Ahn ,  Satoru Yamada ,  Young-Jin Choi ,  Seung-Uk Han ,  Kyo-Suk Chae

IPC分类号： H01L29/792 ,  H01L23/525

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/5256 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.

摘要翻译： 公开了一种半导体器件。 半导体器件包括半导体衬底，第一晶体杂质区，第二晶体杂质区，第三晶体杂质区和绝缘层。 第一至第三晶体杂质区设置在半导体衬底中。 第一至第三节点杂质区域中的每一个具有分别相对于彼此垂直的第一至第三方向的纵向长度，横向长度和厚度。 第一节点杂质区域平行于第二和第三节点杂质区域，其被布置在基本相同的线上。 绝缘层位于半导体衬底中的第一至第三结点杂质区之间。

公开(公告)号：US08653622B2

公开(公告)日：2014-02-18

申请号：US13038117

申请日：2011-03-01

申请人： Woo-Song Ahn ,  Satoru Yamada ,  Young-Jin Choi ,  Seung-Uk Han ,  Kyo-Suk Chae

发明人： Woo-Song Ahn ,  Satoru Yamada ,  Young-Jin Choi ,  Seung-Uk Han ,  Kyo-Suk Chae

IPC分类号： H01L29/792 ,  H01L23/525

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/5256 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.

摘要翻译： 公开了一种半导体器件。 半导体器件包括半导体衬底，第一晶体杂质区，第二晶体杂质区，第三晶体杂质区和绝缘层。 第一至第三晶体杂质区设置在半导体衬底中。 第一至第三节点杂质区域中的每一个具有分别相对于彼此垂直的第一至第三方向的纵向长度，横向长度和厚度。 第一节点杂质区域平行于第二和第三节点杂质区域，其被布置在基本相同的线上。 绝缘层位于半导体衬底中的第一至第三结点杂质区之间。

公开(公告)号：US08823113B2

公开(公告)日：2014-09-02

申请号：US12984762

申请日：2011-01-05

申请人： Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

发明人： Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833

摘要： A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

摘要翻译： 四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。 四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。 设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。 最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。 相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

公开(公告)号：US20120001271A1

公开(公告)日：2012-01-05

申请号：US12984762

申请日：2011-01-05

申请人： Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

发明人： Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833

摘要： A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

摘要翻译： 四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。 四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。 设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。 最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。 相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

公开(公告)号：US09418988B2

公开(公告)日：2016-08-16

申请号：US14461202

申请日：2014-08-15

申请人： Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

发明人： Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833

摘要： A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

摘要翻译： 四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。 四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。 设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。 最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。 相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

公开(公告)号：US08653603B2

公开(公告)日：2014-02-18

申请号：US13028691

申请日：2011-02-16

申请人： Won-Kyung Park ,  Satoru Yamada ,  Young Jin Choi ,  Kyo-Suk Chae

发明人： Won-Kyung Park ,  Satoru Yamada ,  Young Jin Choi ,  Kyo-Suk Chae

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/105 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes a substrate including a memory cell region and a peripheral region and a field pattern including an insulating region disposed on a nitride liner in a trench in the substrate adjacent an active region. The field pattern and the active region extend in parallel through the cell and peripheral regions. The device also includes a transistor in the peripheral region including a source/drain region in the active region. The device further includes an insertion pattern including an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region. Fabrication methods are also described.

摘要翻译： 半导体器件包括：衬底，其包括存储单元区域和周边区域;以及场图案，其包括设置在邻近有源区域的衬底中的沟槽中的氮化物衬垫上的绝缘区域。 场图案和有源区域通过单元和外围区域并行延伸。 该器件还包括在该周边区域中的晶体管，其包括有源区域中的源极/漏极区域。 该装置还包括插入图案，其包括设置在基板中并沿着外围区域中的场图案和有源区域之间的边界延伸的细长导电区域。 还描述了制造方法。

公开(公告)号：US20110198700A1

公开(公告)日：2011-08-18

申请号：US13028691

申请日：2011-02-16

申请人： Won-Kyung Park ,  Satoru Yamada ,  Young Jin Choi ,  Kyo-Suk Chae

发明人： Won-Kyung Park ,  Satoru Yamada ,  Young Jin Choi ,  Kyo-Suk Chae

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/105 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes a substrate including a memory cell region and a peripheral region and a field pattern including an insulating region disposed on a nitride liner in a trench in the substrate adjacent an active region. The field pattern and the active region extend in parallel through the cell and peripheral regions. The device also includes a transistor in the peripheral region including a source/drain region in the active region. The device further includes an insertion pattern including an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region. Fabrication methods are also described.

摘要翻译： 半导体器件包括：衬底，其包括存储单元区域和周边区域;以及场图案，其包括设置在邻近有源区域的衬底中的沟槽中的氮化物衬垫上的绝缘区域。 场图案和有源区域通过单元和外围区域并行延伸。 该器件还包括在该周边区域中的晶体管，其包括有源区域中的源极/漏极区域。 该装置还包括插入图案，其包括设置在基板中并沿着外围区域中的场图案和有源区域之间的边界延伸的细长导电区域。 还描述了制造方法。