公开(公告)号：US06335243B1

公开(公告)日：2002-01-01

申请号：US09016399

申请日：1998-01-30

申请人： Woong-Lim Choi ,  Kyeong-Man Ra

发明人： Woong-Lim Choi ,  Kyeong-Man Ra

IPC分类号： H01L21336

CPC分类号： H01L27/11517 ,  H01L27/115

摘要： A method of fabricating a nonvolatile memory device having a first conductivity type substrate, includes the steps of forming a gate insulating layer on the entire surface of the semiconductor substrate, forming a plurality of floating gate lines on the gate insulating layer, forming first sidewall spacers on both sides of each floating gate, forming a plurality of impurity regions having a second conductivity type in the substrate between the floating gate lines, forming a dielectric layer on the floating gate lines, forming a plurality of control gate lines on the dielectric layer, forming second sidewall spacers on both sides of the control gate lines, selectively etching the dielectric layer and the floating gate lines to form a plurality of floating gates, forming tunneling insulating layers on both sides of the floating gates, and forming a plurality of program lines between the impurity regions.

摘要翻译： 一种制造具有第一导电类型基板的非易失性存储器件的方法包括以下步骤：在半导体衬底的整个表面上形成栅极绝缘层，在栅极绝缘层上形成多个浮置栅极线，形成第一侧壁间隔物 在每个浮置栅极的两侧，在浮置栅极线之间的衬底中形成具有第二导电类型的多个杂质区，在浮置栅极线上形成电介质层，在电介质层上形成多个控制栅极线， 在控制栅极线的两侧形成第二侧壁间隔物，选择性地蚀刻电介质层和浮动栅极线以形成多个浮置栅极，在浮置栅极的两侧形成隧穿绝缘层，并形成多个编程线 杂质区之间。

公开(公告)号：US6121072A

公开(公告)日：2000-09-19

申请号：US35128

申请日：1998-03-05

申请人： Woong-Lim Choi ,  Kyeong-Man Ra

发明人： Woong-Lim Choi ,  Kyeong-Man Ra

IPC分类号： H01L27/112 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L27/115

摘要： A method of fabricating a nonvolatile memory device having a substrate, includes the steps of forming a plurality of bit lines in the substrate, forming a plurality of field oxide layers on the substrate perpendicular to the bit lines, forming a gate insulating layer on an entire surface of the substrate including the bit lines and the field oxide layers, forming a plurality of floating lines on the gate insulating layer between the bit lines, forming a dielectric layer on the entire surface of the semiconductor substrate including the floating line's and the gate insulating layer, forming a plurality of word lines between the field oxide layer perpendicular to the bit lines, forming sidewall spacer at both sides of the word lines, selectively removing the dielectric layer and the floating lines using the word lines and the sidewall spacer as masks to form a plurality of floating gates, forming a tunneling layer at both sides of the floating gates, and forming a plurality of program lines between the bit lines.

摘要翻译： 一种制造具有衬底的非易失性存储器件的方法，包括在衬底中形成多个位线的步骤，在垂直于位线的衬底上形成多个场氧化物层，在整个衬底上形成栅极绝缘层 包括位线和场氧化物层的衬底的表面，在位线之间的栅极绝缘层上形成多条浮动线，在包括浮动线的半导体衬底和栅极绝缘层的整个表面上形成介电层 层，在垂直于位线的场氧化层之间形成多个字线，在字线的两侧形成侧壁间隔物，使用字线和侧壁间隔件作为掩模选择性地去除电介质层和浮动线， 形成多个浮动栅极，在浮动栅极的两侧形成隧道层，并形成多个程序 在位线之间。

公开(公告)号：US6146943A

公开(公告)日：2000-11-14

申请号：US033670

申请日：1998-03-03

申请人： Woong-Lim Choi ,  Kyeong-Man Ra

发明人： Woong-Lim Choi ,  Kyeong-Man Ra

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11517

摘要： A method is provided for fabricating a nonvolatile memory device having a simple stacked stricture with program gates. The method includes forming bitlines of second conductivity type along a first direction separated by a first prescribed distance in a substrate of a first conductivity type and forming first lines on the substrate along a second direction separated from one another by a second prescribed distance. The second direction is substantially perpendicular to the first direction, and the first lines include a first conductive layer on an isolating layer. A gate insulating layer is formed on the substrate and a tunneling insulating layer on the first conductive lines and a second conductive layer is formed on the entire surface. The second conductive layer, the tunneling insulating layer, and the first conductive lines are selectively removed to form second conductive lines along the first direction and program gates. A dielectric film is formed on the second conductive lines and a third conductive layer and an insulating layer are formed on the entire surface. The insulating layer, the third conductive layer, the dielectric film, and the second conductive lines are selectively removed to form word lines in the second direction and floating gates between the first conductive lines. Insulating sidewall spacers are formed on both sides of the patterned insulating layer, the word lines, the dielectric film, and the floating gates and contact holes are formed in the tunneling insulating layer. Then, program lines are formed coupled to the program gates through the contact holes.

摘要翻译： 提供了一种用于制造具有与程序门的简单堆叠狭缝的非易失性存储器件的方法。 该方法包括在第一导电类型的衬底中沿着与第一规定距离分开的第一方向形成第二导电类型的位线，并且沿着沿彼此分开第二规定距离的第二方向在衬底上形成第一线。 第二方向基本上垂直于第一方向，并且第一线包括隔离层上的第一导电层。 在基板上形成栅绝缘层，在整个表面上形成第一导线上的隧道绝缘层和第二导电层。 选择性地去除第二导电层，隧道绝缘层和第一导电线，以沿着第一方向和程序栅极形成第二导电线。 在第二导线上形成电介质膜，在整个表面上形成第三导电层和绝缘层。 选择性地去除绝缘层，第三导电层，电介质膜和第二导电线以在第二方向上形成字线，并且在第一导线之间形成浮动栅极。 在图案化绝缘层的两侧形成绝缘侧壁间隔物，在隧道绝缘层中形成字线，电介质膜，浮栅和接触孔。 然后，通过接触孔将编程线形成为耦合到编程门。

公开(公告)号：US5998829A

公开(公告)日：1999-12-07

申请号：US985679

申请日：1997-12-05

申请人： Woong-Lim Choi ,  Kyeong-Man Ra

发明人： Woong-Lim Choi ,  Kyeong-Man Ra

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L27/115

摘要： A non-volatile memory device and a method of fabricating the same are disclosed. The non-volatile memory device includes a semiconductor substrate having a first conductive type, a plurality of first, second and third impurity regions having a second conductive type in the substrate, a plurality of first insulating layer only on the substrate between the second and third impurity regions, a second insulating layer on the substrate except on the first insulating layer formed, a plurality of floating gate on the first and second insulating layers, a plurality of dielectric layer on the floating gate, a plurality of control gate on the dielectric layer.

摘要翻译： 公开了一种非易失性存储器件及其制造方法。 非易失性存储器件包括具有第一导电类型的半导体衬底，在衬底中具有第二导电类型的多个第一，第二和第三杂质区域，仅在第二和第三衬底之间的衬底上的多个第一绝缘层 杂质区域，除了形成的第一绝缘层之外的基板上的第二绝缘层，在第一和第二绝缘层上的多个浮置栅极，浮置栅极上的多个电介质层，电介质层上的多个控制栅极 。

公开(公告)号：US6038175A

公开(公告)日：2000-03-14

申请号：US251322

申请日：1999-02-17

申请人： Kyeong-Man Ra

发明人： Kyeong-Man Ra

IPC分类号： G11C16/00 ,  G11C16/34 ,  G11C29/00

CPC分类号： G11C29/82 ,  G11C16/344 ,  G11C16/3445

摘要： An erase verifying apparatus includes: a memory cell array including a plurality of main areas and redundant areas having one or more cells, the main areas and redundant areas forming an erase block, a wordline circuit for controlling wordlines in the memory cell array, a redundancy control unit for storing redundancy information, a data buffer for loading replacement information from the redundancy control unit, a column selector for selecting a column in the memory cell array, a sense amplifier for sensing an output from the selected cell, and a controller for controlling all operations, and an erase verifying method includes the steps of: initializing the data buffer, loading the redundancy information stored in the redundancy control unit to the data buffer, selecting a certain erase block and erasing the cell data of the selected erase block by using the wordline circuit, selecting the cells of the selected erase block sequentially, checking whether the cell of the data buffer corresponding to the selected cell is replaced by the redundancy, and checking the output from the sense amplifier when the cell of the data buffer is not replaced by the redundancy.

摘要翻译： 擦除验证装置包括：存储单元阵列，包括多个主区域和具有一个或多个单元的冗余区域，主区域和形成擦除块的冗余区域，用于控制存储单元阵列中的字线的字线电路，冗余 用于存储冗余信息的控制单元，用于从冗余控制单元装载替换信息的数据缓冲器，用于选择存储单元阵列中的列的列选择器，用于感测所选单元的输出的读出放大器，以及用于控制 所有操作和擦除验证方法包括以下步骤：初始化数据缓冲器，将存储在冗余控制单元中的冗余信息加载到数据缓冲器，选择某个擦除块并通过使用擦除块擦除所选擦除块的单元数据 字线电路，顺序地选择所选择的擦除块的单元，检查数据缓冲器的单元是否可以 响应所选择的单元被冗余代替，并且当数据缓冲器的单元不被冗余代替时，检查来自读出放大器的输出。

公开(公告)号：US06323671B1

公开(公告)日：2001-11-27

申请号：US09291309

申请日：1999-04-15

申请人： Kyeong-Man Ra

发明人： Kyeong-Man Ra

IPC分类号： G11C1134

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/5006

摘要： A charge gain stress test circuit for a nonvolatile memory and a test method using the same according to the present invention allow a maximum size of a voltage used for a stress lower than a voltage applied in a normal operation. The preferred embodiment sufficiently increases an absolute value of an applicable stress voltage by using a reference current to control a stress voltage value without burdening the peripheral circuits. The preferred embodiment optimizes a stress time, namely the test time.

摘要翻译： 根据本发明的用于非易失性存储器的充电增益应力测试电路和使用该电路的测试方法允许用于低于在正常操作中施加的电压的应力的电压的最大尺寸。 优选实施例通过使用参考电流来充分地增加可应用的应力电压的绝对值来控制应力电压值而不会对外围电路造成负担。 优选实施例优化了应力时间，即测试时间。

公开(公告)号：US06480018B2

公开(公告)日：2002-11-12

申请号：US09973087

申请日：2001-10-10

申请人： Kyeong-Man Ra

发明人： Kyeong-Man Ra

IPC分类号： G01R3126

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/5006

摘要： A charge gain stress test circuit for a nonvolatile memory and a test method using the same according to the present invention allow a maximum size of a voltage used for a stress lower than a voltage applied in a normal operation. The preferred embodiment sufficiently increases an absolute value of an applicable stress voltage by using a reference current to control a stress voltage value without burdening the peripheral circuits. The preferred embodiment optimizes a stress time, namely the test time.