公开(公告)号：US20230251620A1

公开(公告)日：2023-08-10

申请号：US17665860

申请日：2022-02-07

Applicant: X Development LLC

Inventor： Raj Apte ,  Cyrus Behroozi ,  Zhigang Pan ,  Dino Ruic

IPC: G05B19/18 ,  G05B13/02

CPC classification number: G05B19/188 ,  G05B13/0265 ,  G05B2219/45031

Abstract: Systems, computer-implemented methods, and instructions encoded in machine-accessible storage media are provided for determining manufacturability of an integrated circuit layout. A computer-implemented method includes receiving a layout describing the integrated circuit to be manufactured by a semiconductor manufacturing process. The method also includes generating a differentiable manufacturability parameter as an output of a machine learning model using the layout, the machine learning model being trained to generate the differentiable manufacturability parameter. The differentiable manufacturability parameter describes the manufacturability of the integrated circuit by the semiconductor manufacturing process.

公开(公告)号：US11675960B2

公开(公告)日：2023-06-13

申请号：US17516476

申请日：2021-11-01

Applicant: X Development LLC

Inventor： Raj Apte ,  Cyrus Behroozi ,  Kathryn Heal ,  Owen Lewis ,  Zhigang Pan ,  Dino Ruic

IPC: G06F30/398 ,  G06F30/323 ,  G06F30/27

CPC classification number: G06F30/398 ,  G06F30/27 ,  G06F30/323

Abstract: Embodiments of a system and method for generating integrated circuit layouts are described herein. A computer implemented method for generating integrated circuit layouts includes receiving a first layout for an integrated circuit, segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout, identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit, generating a transformation of the non-compliant patch using a machine learning model, and generating a second layout using the transformation and the first layout, where the second layout is compliant with the design rule.

公开(公告)号：US20230214571A1

公开(公告)日：2023-07-06

申请号：US17570019

申请日：2022-01-06

Applicant: X Development LLC

Inventor： Raj Apte ,  Zhigang Pan ,  Dino Ruic ,  Cyrus Behroozi

IPC: G06F30/394 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F2119/18

Abstract: A computer-implemented method for integrated circuit routing is described. The computer-implemented method comprising receiving a description of interconnected terminals of an integrated circuit with a wiring route electrically coupling the interconnected terminals and configuring a simulated environment defined via a plurality of voxels based on the description. The individual voxels included in the plurality of voxels each correspond to a spatial representation for a corresponding region of a layout associated with the integrated circuit. The computer-implemented method further includes determining local contributions of the individual voxels to a characteristic metric of the integrated circuit based on an electromagnetic simulation of the integrated circuit and revising the wiring route based on the local contributions of the individual voxels.

公开(公告)号：US20240370630A1

公开(公告)日：2024-11-07

申请号：US18772363

申请日：2024-07-15

Applicant: X Development LLC

Inventor： Raj Apte ,  Zhigang Pan ,  Dino Ruic ,  Cyrus Behroozi

IPC: G06F30/394 ,  G06F30/392 ,  G06F119/18

Abstract: A computer-implemented method for integrated circuit routing is described. The computer-implemented method comprising receiving a description of interconnected terminals of an integrated circuit with a wiring route electrically coupling the interconnected terminals and configuring a simulated environment defined via a plurality of voxels based on the description. The individual voxels included in the plurality of voxels each correspond to a spatial representation for a corresponding region of a layout associated with the integrated circuit. The computer-implemented method further includes determining local contributions of the individual voxels to a characteristic metric of the integrated circuit based on an electromagnetic simulation of the integrated circuit and revising the wiring route based on the local contributions of the individual voxels.

公开(公告)号：US12067339B2

公开(公告)日：2024-08-20

申请号：US17570019

申请日：2022-01-06

Applicant: X Development LLC

Inventor： Raj Apte ,  Zhigang Pan ,  Dino Ruic ,  Cyrus Behroozi

IPC: G06F30/394 ,  G06F30/392 ,  G06F119/18

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F2119/18

Abstract: A computer-implemented method for integrated circuit routing is described. The computer-implemented method comprising receiving a description of interconnected terminals of an integrated circuit with a wiring route electrically coupling the interconnected terminals and configuring a simulated environment defined via a plurality of voxels based on the description. The individual voxels included in the plurality of voxels each correspond to a spatial representation for a corresponding region of a layout associated with the integrated circuit. The computer-implemented method further includes determining local contributions of the individual voxels to a characteristic metric of the integrated circuit based on an electromagnetic simulation of the integrated circuit and revising the wiring route based on the local contributions of the individual voxels.

公开(公告)号：US20230138706A1

公开(公告)日：2023-05-04

申请号：US17516476

申请日：2021-11-01

Applicant: X Development LLC

Inventor： Raj Apte ,  Cyrus Behroozi ,  Kathryn Heal ,  Owen Lewis ,  Zhigang Pan ,  Dino Ruic

IPC: G06F30/398 ,  G06F30/27 ,  G06F30/323

Abstract: Embodiments of a system and method for generating integrated circuit layouts are described herein. A computer implemented method for generating integrated circuit layouts includes receiving a first layout for an integrated circuit, segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout, identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit, generating a transformation of the non-compliant patch using a machine learning model, and generating a second layout using the transformation and the first layout, where the second layout is compliant with the design rule.