公开(公告)号：US10978169B2

公开(公告)日：2021-04-13

申请号：US15462397

申请日：2017-03-17

Applicant: XEROX CORPORATION

Inventor： Markus Rudolf Silvestri ,  Kamran Uz Zaman ,  Christopher P. Caporale ,  Jimmy E. Kelly ,  John M. Scharr ,  Alberto Rodriguez ,  Dennis J. Prosser

IPC: G11C29/10 ,  G11C11/22 ,  G06F3/06 ,  G11C29/20 ,  G11C29/44 ,  G11C29/04

Abstract: A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example, prior to a read or write cycle, during functional testing of the memory array, etc. In one implementation, the memory array is read and the data set including a data bit from each cell is stored in a register. A solid logic 0's pattern is written into the memory array, and each cell is read. If no cell returns a logic 1, it is determined that the memory array is properly connected and the register data values are written to the memory array. If one or more cells returns a logic 1, it is determined that the memory array is improperly connected, the register data values are written to the memory array, and the memory array is removed and reinstalled.

公开(公告)号：US20200335149A1

公开(公告)日：2020-10-22

申请号：US16881745

申请日：2020-05-22

Applicant: XEROX CORPORATION

Inventor： Christopher P. Caporale ,  Alberto Rodriguez ,  Markus R. Silvestri ,  Terry L. Street ,  Ron Edward Dufort

IPC: G11C11/22 ,  G11C11/56

Abstract: A computer-implemented method for writing to a printed memory device is disclosed. The computer-implemented method includes determining, by a microcontroller, a first encoding scheme from among a plurality of encoding schemes to write a first data portion from among a plurality of data portions, wherein the first encoding scheme comprises a first voltage and a first pulse width to be used to write the first data portion; providing, by the microcontroller, the first encoding scheme to an application-specific integrated circuit (ASIC); selecting, by the ASIC, a first target memory cell of the printed memory device corresponding to a first word line and a first bit line for the first data portion to be written; and writing, by the ASIC, the first data portion to the first target memory cell using the first encoding scheme.

公开(公告)号：US09886571B2

公开(公告)日：2018-02-06

申请号：US15044406

申请日：2016-02-16

Applicant: XEROX CORPORATION

Inventor： Christopher P. Caporale ,  Alberto Rodriguez ,  Scott Jonathan Bell ,  John M. Scharr

IPC: G06F21/79 ,  G06F21/44 ,  G06F21/85 ,  B41J2/175 ,  B41J29/393 ,  G06F3/12 ,  H04L29/06

CPC classification number: G06F21/44 ,  B41J2/1753 ,  B41J2/17546 ,  B41J29/02 ,  B41J29/393 ,  G06F3/1239 ,  G06F21/79 ,  G06F21/85 ,  H04L63/0876

Abstract: A component subsystem and a method for authenticating the component subsystem. The component subsystem may be installed in a host device. The method can include an authentication protocol, wherein the host device sends a test voltage value to the component subsystem which, in turn, generates a test voltage based on the test voltage value. The test voltage is applied to a test cell that includes a wordline, a bitline, and a memory film. A response voltage is read from the bitline and compared to an expected value. If the response voltage matches the expected value, host device and/or component subsystem functionality is enabled. If the response voltage does not match the expected value, the host device and/or component subsystem functionality is disabled.

公开(公告)号：US20170235939A1

公开(公告)日：2017-08-17

申请号：US15044406

申请日：2016-02-16

Applicant: XEROX CORPORATION

Inventor： Christopher P. Caporale ,  Alberto Rodriguez ,  Scott Jonathan Bell ,  John M. Scharr

IPC: G06F21/44 ,  G06F21/85

CPC classification number: G06F21/44 ,  B41J2/1753 ,  B41J2/17546 ,  B41J29/02 ,  B41J29/393 ,  G06F3/1239 ,  G06F21/79 ,  G06F21/85 ,  H04L63/0876

Abstract: A component subsystem and a method for authenticating the component subsystem. The component subsystem may be installed in a host device. The method can include an authentication protocol, wherein the host device sends a test voltage value to the component subsystem which, in turn, generates a test voltage based on the test voltage value. The test voltage is applied to a test cell that includes a wordline, a bitline, and a memory film. A response voltage is read from the bitline and compared to an expected value. If the response voltage matches the expected value, host device and/or component subsystem functionality is enabled. If the response voltage does not match the expected value, the host device and/or component subsystem functionality is disabled.

公开(公告)号：US10748597B1

公开(公告)日：2020-08-18

申请号：US16389535

申请日：2019-04-19

Applicant: XEROX CORPORATION

Inventor： Christopher P. Caporale ,  Alberto Rodriguez ,  Markus R. Silvestri ,  Terry L. Street ,  Ron Edward Dufort

IPC: G11C11/22 ,  G11C11/56

Abstract: A computer-implemented method for writing to and reading from a printed memory device is provided. Data to be written to the printed memory device is segmented into a plurality of data portions. Each data portion of the plurality of data portions is written to a memory cell of the printed memory as a tuple using a determined encoding scheme that is characterized by a voltage and a pulse width. The voltage that is used for the encoding scheme is within a predetermined polarization regime of the printed memory device. Tuples of data can be read from memory cells of the printed memory using a decoding scheme.

公开(公告)号：US20200234752A1

公开(公告)日：2020-07-23

申请号：US16250908

申请日：2019-01-17

Applicant: XEROX CORPORATION

Inventor： Christopher P. Caporale ,  Alberto Rodriguez ,  Markus R. Silvestri ,  Terry L. Street

IPC: G11C11/22 ,  G11C7/18 ,  G11C8/14

Abstract: A computer-implemented method for testing a printed memory device is provided. The computer-implemented method includes performing, by a controller, a first read operation on a cell of the printed memory device; performing, by the controller, a second read operation on the cell; converting, by the controller, a first result of the first read operation and a second results of the second read operation to a first digital value and a second digital value, respectively; comparing, by the controller, the first digital value and the second digital value to a first predetermined threshold and a second predetermined threshold, respectively, wherein the first predetermined threshold is a low threshold and the second predetermined threshold is a high threshold; and providing, by the controller, a result of the test for the printed memory device based on the comparing.

公开(公告)号：USRE48938E1

公开(公告)日：2022-02-22

申请号：US16358447

申请日：2019-03-19

Applicant: XEROX CORPORATION

Inventor： Christopher P. Caporale ,  Alberto Rodriguez ,  Scott Jonathan Bell ,  John M. Scharr

IPC: G06F21/44 ,  B41J2/175 ,  B41J29/02 ,  B41J29/393 ,  G06F3/12 ,  G06F21/79 ,  G06F21/85 ,  H04L29/06

Abstract: A component subsystem and a method for authenticating the component subsystem. The component subsystem may be installed in a host device. The method can include an authentication protocol, wherein the host device sends a test voltage value to the component subsystem which, in turn, generates a test voltage based on the test voltage value. The test voltage is applied to a test cell that includes a wordline, a bitline, and a memory film. A response voltage is read from the bitline and compared to an expected value. If the response voltage matches the expected value, host device and/or component subsystem functionality is enabled. If the response voltage does not match the expected value, the host device and/or component subsystem functionality is disabled.

公开(公告)号：US10311264B1

公开(公告)日：2019-06-04

申请号：US15967255

申请日：2018-04-30

Applicant: XEROX CORPORATION

Inventor： Christopher P. Caporale ,  Alberto Rodriguez

IPC: G06K7/10

Abstract: A radio frequency identification (RFID) technique is disclosed. The technique includes a printed RFID antenna array including at least three printed RFID antenna elements and an RFID reader device with at least one RFID reader antenna sized to transmit excitation energy to a number N>1 of printed RFID antenna elements of the printed RFID antenna array, where N is less than a total number of printed RFID antenna elements of the printed RFID antenna array. The RFID reader antenna is configured to receive a plurality of compound signals from respective subarrays consisting of N of the printed RFID antenna elements of the printed RFID antenna array. The RFID reader device also includes a demodulator, a decoder, and an output interface.

公开(公告)号：US20180268916A1

公开(公告)日：2018-09-20

申请号：US15462397

申请日：2017-03-17

Applicant: XEROX CORPORATION

Inventor： Markus Rudolf Silvestri ,  Kamran Uz Zaman ,  Christopher P. Caporale ,  Jimmy E. Kelly ,  John M. Scharr ,  Alberto Rodriguez ,  Dennis J. Prosser

IPC: G11C29/10 ,  G11C11/22 ,  G06F3/06

CPC classification number: G11C29/10 ,  G11C11/221 ,  G11C29/20 ,  G11C29/44 ,  G11C2029/4402

Abstract: A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example, prior to a read or write cycle, during functional testing of the memory array, etc. In one implementation, the memory array is read and the data set including a data bit from each cell is stored in a register. A solid logic 0's pattern is written into the memory array, and each cell is read. If no cell returns a logic 1, it is determined that the memory array is properly connected and the register data values are written to the memory array. If one or more cells returns a logic 1, it is determined that the memory array is improperly connected, the register data values are written to the memory array, and the memory array is removed and reinstalled.