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公开(公告)号:US20230366929A1
公开(公告)日:2023-11-16
申请号:US17742363
申请日:2022-05-11
Applicant: XILINX, INC.
Inventor: Albert Shih-Huai LIN , Niravkumar PATEL , Amitava MAJUMDAR , Jane Wang SOWARDS
IPC: G01R31/3185 , G01R31/317
CPC classification number: G01R31/318555 , G01R31/318572 , G01R31/31727
Abstract: An integrated circuit (IC) chip device includes testing interface circuitry and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.
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2.
公开(公告)号:US20240356544A1
公开(公告)日:2024-10-24
申请号:US18138008
申请日:2023-04-21
Applicant: XILINX, INC.
Inventor: Rambabu NERUKONDA , Albert Shih-Huai LIN , Sreedhar BORRA , Rajat CHADHA , Amitava MAJUMDAR
Abstract: Embodiments herein describe an integrated circuit (IC) device that includes a multi-protocol, multi-cast, and multi-root network-on-chip (NoC) with dynamic resource allocation (DFxNoC). A DFxNoC may include a plurality of end-points (EPs) that include functional circuitry, first and second root devices, and a bus network that includes multi-port switch circuits and a network of fixed links amongst the multi-port switch circuits, the root devices, and the EPs, where the root devices output respective first and second clocks, and where the multi-port switch circuits are dynamically configurable to route the first and second clocks to respective first and second selectable sets of one or more of the EPs over the network of fixed links.
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