公开(公告)号：US20230366929A1

公开(公告)日：2023-11-16

申请号：US17742363

申请日：2022-05-11

Applicant: XILINX, INC.

Inventor： Albert Shih-Huai LIN ,  Niravkumar PATEL ,  Amitava MAJUMDAR ,  Jane Wang SOWARDS

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318555 ,  G01R31/318572 ,  G01R31/31727

Abstract: An integrated circuit (IC) chip device includes testing interface circuitry and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.

公开(公告)号：US20240356544A1

公开(公告)日：2024-10-24

申请号：US18138008

申请日：2023-04-21

Applicant: XILINX, INC.

Inventor： Rambabu NERUKONDA ,  Albert Shih-Huai LIN ,  Sreedhar BORRA ,  Rajat CHADHA ,  Amitava MAJUMDAR

IPC: H03K17/56 ,  H04L12/40

CPC classification number: H03K17/56 ,  H04L12/40

Abstract: Embodiments herein describe an integrated circuit (IC) device that includes a multi-protocol, multi-cast, and multi-root network-on-chip (NoC) with dynamic resource allocation (DFxNoC). A DFxNoC may include a plurality of end-points (EPs) that include functional circuitry, first and second root devices, and a bus network that includes multi-port switch circuits and a network of fixed links amongst the multi-port switch circuits, the root devices, and the EPs, where the root devices output respective first and second clocks, and where the multi-port switch circuits are dynamically configurable to route the first and second clocks to respective first and second selectable sets of one or more of the EPs over the network of fixed links.

公开(公告)号：US20230085149A1

公开(公告)日：2023-03-16

申请号：US17477185

申请日：2021-09-16

Applicant: XILINX, INC.

Inventor： Pramod BHARDWAJ ,  Sarosh I. AZAD ,  Wern-Yan KOE ,  Amitava MAJUMDAR

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/28

Abstract: In one example, an integrated circuit (IC) is provided that includes data circuitry and a processing circuitry. The data circuitry is configured to provide data to be transferred to a different circuitry within the IC or to an external IC. The processing circuitry is configured to: read the data provided by the data circuitry before it is transferred to the different circuitry or the external IC; calculate a first signature for the data; attach the first signature to the data; calculate, after transferring the data to the different circuitry or the external IC, a second signature for the data; extract the first signature corresponding to the data; compare the first signature to the second signature; and generate a signal based on a comparison of the first signature to the second signature.

公开(公告)号：US20230290189A1

公开(公告)日：2023-09-14

申请号：US17691896

申请日：2022-03-10

Applicant: XILINX, INC.

Inventor： Yanran CHEN ,  Sagheer AHMAD ,  Amitava MAJUMDAR ,  Pramod BHARDWAJ

IPC: G07C5/00 ,  G06F11/10 ,  H04W4/48

CPC classification number: G07C5/008 ,  G06F11/1004 ,  H04W4/48

Abstract: Embodiments herein describe wrapping non-safety compliant hardware resources with error detection checking to satisfy a safety standard. Doing so permits non-safety compliant hardware to be used to perform one or more tasks in a system that, as a whole, satisfies a particular safety standard (e.g., one of the ASIL QM, A, B, C, and D grades).