公开(公告)号：US12068257B1

公开(公告)日：2024-08-20

申请号：US17136721

申请日：2020-12-29

Applicant: XILINX, INC.

Inventor： Myongseob Kim ,  Henley Liu ,  Yun Wu ,  Cheang Whang Chang

IPC: H01L23/552 ,  H01L21/50 ,  H01L23/528

CPC classification number: H01L23/552 ,  H01L21/50 ,  H01L23/528

Abstract: Some examples described herein relate to protecting an integrated circuit (IC) structure from imaging or access. In an example, an IC structure includes a semiconductor substrate, an electromagnetic radiation blocking layer, and a support substrate. The semiconductor substrate has a circuit disposed on a front side of the semiconductor substrate. The electromagnetic radiation blocking layer is disposed on a backside of the semiconductor substrate opposite from the front side of the semiconductor substrate. The support substrate is bonded to the semiconductor substrate. The electromagnetic radiation blocking layer is disposed between the semiconductor substrate and the support substrate.

公开(公告)号：US11205639B2

公开(公告)日：2021-12-21

申请号：US16798267

申请日：2020-02-21

Applicant: XILINX, INC.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang Whang Chang

IPC: H01L21/50 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

公开(公告)号：US12045469B2

公开(公告)日：2024-07-23

申请号：US18082223

申请日：2022-12-15

Applicant: XILINX, INC.

Inventor： Kumar Rahul ,  John J. Wuu ,  Santosh Yachareni ,  Nui Chong ,  Cheang Whang Chang

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

Abstract: A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

公开(公告)号：US11901338B2

公开(公告)日：2024-02-13

申请号：US17515354

申请日：2021-10-29

Applicant: XILINX, INC.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang Whang Chang

IPC: G01R31/28 ,  H01L21/66 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L22/32 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2225/06596

Abstract: An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.