公开(公告)号：US11875100B1

公开(公告)日：2024-01-16

申请号：US17339232

申请日：2021-06-04

Applicant: XILINX, INC.

Inventor： Satish Sivaswamy ,  Ashot Shakhkyan ,  Nitin Deshmukh ,  Garik Mkrtchyan ,  Guenter Stenz ,  Bhasker Pinninti

IPC: G06F30/3947 ,  G06F9/355 ,  G06F9/50 ,  G06F30/347

CPC classification number: G06F30/3947 ,  G06F9/3555 ,  G06F9/5061 ,  G06F30/347

Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.

公开(公告)号：US09881112B1

公开(公告)日：2018-01-30

申请号：US14677868

申请日：2015-04-02

Applicant: Xilinx, Inc.

Inventor： Fan Zhang ,  Anup K. Sultania ,  Guenter Stenz

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Vectorless dynamic power estimation for a circuit design may include forming, using a processor, a complex basic element within the circuit design, determining, using the processor, initial toggle rates for basic elements within the circuit design, and determining, using the processor, an initial toggle rate for the complex basic element. Vectorless dynamic power estimation further may include generating, using the processor, final toggle rates by updating the initial toggle rates according to a control signal analysis and calculating, using the processor, dynamic power dissipation for the circuit design using the final toggle rates.

公开(公告)号：US10891413B1

公开(公告)日：2021-01-12

申请号：US16704762

申请日：2019-12-05

Applicant: Xilinx, Inc.

Inventor： Paul D. Kundarewich ,  Grigor S. Gasparyan ,  Mehrdad Eslami Dehkordi ,  Guenter Stenz

IPC: G06F30/333 ,  G06F30/392 ,  G06F30/327 ,  G06F111/04

Abstract: Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.

公开(公告)号：US10416232B1

公开(公告)日：2019-09-17

申请号：US16012535

申请日：2018-06-19

Applicant: Xilinx, Inc.

Inventor： Guenter Stenz ,  Parivallal Kannan

IPC: G01R31/317 ,  G01R31/3183 ,  H03K19/177 ,  G01R31/3185 ,  G11C29/00

Abstract: Implementing a circuit design may include detecting, using computer hardware, a net of the circuit design with a hold timing violation, generating, using the computer hardware, a list including each load of the net, and filtering, using the computer hardware, the list based on predetermined criteria by, at least in part, removing each load from the list determined to be non-critical with respect to hold timing. Using the computer hardware, the circuit design is modified by inserting a flip-flop in the net to drive each load remaining on the list, clocking the flip-flop with a clock signal of a start point or an end point of a path traversing the net, and triggering the flip-flop with an opposite clock edge compared to the start point or the end point.

公开(公告)号：US11106851B1

公开(公告)日：2021-08-31

申请号：US16805604

申请日：2020-02-28

Applicant: Xilinx, Inc.

Inventor： Paul D. Kundarewich ,  Grigor S. Gasparyan ,  Mehrdad Eslami Dehkordi ,  Guenter Stenz ,  Xiao Dong

IPC: G06F30/392

Abstract: Disclosed approaches for processing a circuit design include interrupting processing of a circuit design by an electronic design automation (EDA) tool at a selected phase of processing. The tool serializes EDA state data into serialized state data while processing is interrupted and writes the serialized state data for subsequent restoration of tool state. To resume processing at the point of interruption, the EDA tool can read the serialized state data and deserialize the serialized state data. The EDA tool bypasses one or more phases of processing after reading the serialized state data and thereafter resumes processing of the circuit design.

公开(公告)号：US11003827B1

公开(公告)日：2021-05-11

申请号：US16796855

申请日：2020-02-20

Applicant: XILINX, INC.

Inventor： Paul D. Kundarewich ,  Grigor S. Gasparyan ,  Mehrdad Eslami Dehkordi ,  Guenter Stenz ,  Zhaoxuan Shen ,  Amish Pandya

IPC: G06F30/392 ,  G06F111/04

Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed by one or more processors, cause the one or more processors to perform operations. The operations include: generating, using the one or more processors, a plurality of child processes according to a number of programmable dies of the multi-die device, each of the plurality of child processes corresponding to a respective programmable die of the multi-die device, wherein the plurality of child processes execute on different processors; partitioning a design for the multi-die device into a plurality of portions, each of the portions to be used to configure one of the programmable dies of the multi-die device; transmitting the plurality of portions of the design to the plurality of child processes for placement; and receiving placements from the plurality of child processes.