公开(公告)号：US09529957B1

公开(公告)日：2016-12-27

申请号：US14606988

申请日：2015-01-27

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Xiao Dong ,  Marvin Tom

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5054

Abstract: Placing a circuit design may include partitioning circuit elements of the circuit design into circuit element sets and grouping bins of an integrated circuit into bin sets. The bins include circuit elements of the circuit design from an initial placement. Placing a circuit design also may include determining a dependency connectivity metric for the circuit elements and, using a processor, selectively relocating circuit elements concurrently, for a plurality of iterations, using a cost metric for relocating the circuit elements and using an order of processing the circuit elements determined from the bin sets, the circuit element sets, and the dependency connectivity metrics.

Abstract translation: 放置电路设计可以包括将电路设计的电路元件分成电路元件组，并将集成电路的盒分组成箱组。 该箱包括从初始放置的电路设计的电路元件。 放置电路设计还可以包括确定电路元件的依赖性连接度量，并且使用处理器，使用用于重新定位电路元件的成本度量并使用处理顺序来选择性地重新定位电路元件，用于多个迭代 从箱组确定的电路元件，电路元件组和依赖性连接度量。

公开(公告)号：US10853541B1

公开(公告)日：2020-12-01

申请号：US16399661

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Abhishek Joshi ,  Grigor S. Gasparyan ,  Aditya Chaubal ,  Sridhar Kirshnamurthy ,  Xiao Dong

IPC: G06F30/327 ,  G06F30/331 ,  G06F30/34 ,  G06F13/40 ,  G06F15/78

Abstract: Some examples described herein relate to global mapping of program nodes of a netlist of an application. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to obtain a netlist of an application. The netlist contains program nodes and respective edges between the program nodes. The application is to be implemented on a device comprising an array of data processing engines. The processor is also configured to execute the instruction code to generate a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generate a detailed mapping of the program nodes based on the global mapping; and translate the detailed mapping to a file.

公开(公告)号：US11106851B1

公开(公告)日：2021-08-31

申请号：US16805604

申请日：2020-02-28

Applicant: Xilinx, Inc.

Inventor： Paul D. Kundarewich ,  Grigor S. Gasparyan ,  Mehrdad Eslami Dehkordi ,  Guenter Stenz ,  Xiao Dong

IPC: G06F30/392

Abstract: Disclosed approaches for processing a circuit design include interrupting processing of a circuit design by an electronic design automation (EDA) tool at a selected phase of processing. The tool serializes EDA state data into serialized state data while processing is interrupted and writes the serialized state data for subsequent restoration of tool state. To resume processing at the point of interruption, the EDA tool can read the serialized state data and deserialize the serialized state data. The EDA tool bypasses one or more phases of processing after reading the serialized state data and thereafter resumes processing of the circuit design.

公开(公告)号：US10783295B1

公开(公告)日：2020-09-22

申请号：US16399493

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Xiao Dong ,  Grigor S. Gasparyan ,  Abhishek Joshi

IPC: G06F30/00 ,  G06F30/327 ,  G06F30/34

Abstract: An example method for compiling includes, by a processor-based system: obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; partitioning the netlist into a plurality of partitions; for each of the plurality of partitions: generating a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generating a detailed mapping of the program nodes based on the global mapping; and translating the detailed mapping for each of the plurality of partitions to a file.

公开(公告)号：US10108773B1

公开(公告)日：2018-10-23

申请号：US15350957

申请日：2016-11-14

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Xiao Dong ,  Xiaojian Yang

IPC: G06F17/50

Abstract: Partitioning a circuit design can include determining, using a processor, a target area utilization and a target cut utilization by iterating over a range of timing violations and determining, using the processor, a worst allowed timing violation based upon the target area utilization and the target cut utilization. Circuit elements of the circuit design can be assigned to partitions, using the processor, for implementation of the circuit design in a multi-die integrated circuit based upon a partition cost calculated using the target area utilization, the target cut utilization, and the worst allowed timing violation.