公开(公告)号：US11501142B1

公开(公告)日：2022-11-15

申请号：US16374451

申请日：2019-04-03

Applicant: Xilinx, Inc.

Inventor： Victor J. Wu ,  Poching Sun ,  Thomas A. Branca ,  Justin Thant Hsin Oo

IPC: G06N3/063 ,  G06F9/30 ,  G06F3/06 ,  G06F9/38

Abstract: A download dispatch circuit initiates download of an input tile of an input feature map in response to a source buffer of two or more source buffers being available for the input tile, and indicates that the input tile is available in response to completion of the download. An operation dispatch circuit initiates a neural network operation on the input tile in response to the input tile being available and a first destination buffer of two or more destination buffers being available for an output tile of an output feature map, and indicates that the output tile is available in response to completion of the neural network operation. An upload dispatch circuit initiates upload of the output tile to the output feature map in response to the output tile being available, and indicates that the first destination buffer is available in response to completion of the upload.

公开(公告)号：US11196715B2

公开(公告)日：2021-12-07

申请号：US16513218

申请日：2019-07-16

Applicant: XILINX, INC.

Inventor： Anujan Varma ,  Poching Sun ,  Chuan Cheng Pan ,  Suchithra Ravi

IPC: H04L29/06 ,  G06F1/3287 ,  G06F21/60 ,  G06F21/64

Abstract: A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to process a signature of the portion and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice-aggregated cryptographic slice.

公开(公告)号：US11194490B1

公开(公告)日：2021-12-07

申请号：US15956594

申请日：2018-04-18

Applicant: Xilinx, Inc.

Inventor： Ravi Sunkavalli ,  Victor J. Wu ,  Poching Sun

IPC: G06F3/06 ,  G06F7/523 ,  G06F16/901

Abstract: A circuit arrangement includes a memory circuit, data upload circuitry, data formatting circuitry, and a systolic array (SA). The data upload circuitry inputs a multi-dimensional data set and stores the multi-dimensional data set in the memory circuit. The data formatting circuitry reads subsets of the multi-dimensional data set from the memory circuit. The data formatting circuitry arranges data elements of the subsets into data streams, and outputs data elements in the data streams in parallel. The SA includes rows and columns of multiply-and-accumulate (MAC) circuits. The SA inputs data elements of the data streams to columns of MAC circuits in parallel, inputs filter values to rows of MAC circuits in parallel, and computes an output feature map from the data streams and the filter values.