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    CUSTOMIZABLE MULTI QUEUE DMA INTERFACE
    1.
    发明申请
    CUSTOMIZABLE MULTI QUEUE DMA INTERFACE 审中-公开

    公开(公告)号：US20190243781A1

    公开(公告)日：2019-08-08

    申请号：US15892266

    申请日：2018-02-08

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S Thyamagondlu ,  Darren Jue ,  Tao Yu ,  John West ,  Hanh Hoang ,  Ravi Sunkavalli

    IPC: G06F12/1081

    CPC classification number: G06F12/1081 ,  G06F2212/621 ,  G06F2213/28

    Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

    Data formatter for convolution
    4.
    发明授权
    Data formatter for convolution 有权

    公开(公告)号：US11194490B1

    公开(公告)日：2021-12-07

    申请号：US15956594

    申请日：2018-04-18

    Applicant: Xilinx, Inc.

    Inventor： Ravi Sunkavalli ,  Victor J. Wu ,  Poching Sun

    IPC: G06F3/06 ,  G06F7/523 ,  G06F16/901

    Abstract: A circuit arrangement includes a memory circuit, data upload circuitry, data formatting circuitry, and a systolic array (SA). The data upload circuitry inputs a multi-dimensional data set and stores the multi-dimensional data set in the memory circuit. The data formatting circuitry reads subsets of the multi-dimensional data set from the memory circuit. The data formatting circuitry arranges data elements of the subsets into data streams, and outputs data elements in the data streams in parallel. The SA includes rows and columns of multiply-and-accumulate (MAC) circuits. The SA inputs data elements of the data streams to columns of MAC circuits in parallel, inputs filter values to rows of MAC circuits in parallel, and computes an output feature map from the data streams and the filter values.

    Customizable multi queue DMA interface
    5.
    发明授权
    Customizable multi queue DMA interface 有权

    公开(公告)号：US10983920B2

    公开(公告)日：2021-04-20

    申请号：US15892266

    申请日：2018-02-08

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S Thyamagondlu ,  Darren Jue ,  Tao Yu ,  John West ,  Hanh Hoang ,  Ravi Sunkavalli

    IPC: G06F12/1081

    Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

    Cryptographic system
    6.
    发明授权
    Cryptographic system 有权

    公开(公告)号：US10659437B1

    公开(公告)日：2020-05-19

    申请号：US16144705

    申请日：2018-09-27

    Applicant: Xilinx, Inc.

    Inventor： Ravi Sunkavalli ,  Anujan Varma ,  Chuan Cheng Pan ,  Patrick C. McCarthy ,  Hanh Hoang

    IPC: H04L29/06

    Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit. The encryption circuit encrypts the plaintext input packet based on the first cryptographic parameters, and the decryption circuit decrypts the ciphertext input packet based on the second cryptographic parameters.

    MULTI-HOST DIRECT MEMORY ACCESS SYSTEM FOR INTEGRATED CIRCUITS
    9.
    发明申请
    MULTI-HOST DIRECT MEMORY ACCESS SYSTEM FOR INTEGRATED CIRCUITS 有权

    公开(公告)号：US20220092010A1

    公开(公告)日：2022-03-24

    申请号：US17457576

    申请日：2021-12-03

    Applicant: Xilinx, Inc.

    Inventor： Chandrasekhar S. Thyamagondlu ,  Darren Jue ,  Ravi Sunkavalli ,  Akhil Krishnan ,  Tao Yu ,  Kushagra Sharma

    IPC: G06F13/28 ,  G06F13/24

    Abstract: A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.

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