公开(公告)号：US11201095B1

公开(公告)日：2021-12-14

申请号：US16549801

申请日：2019-08-23

Applicant: XILINX, INC.

Inventor： Ronilo Boja ,  Inderjit Singh ,  Gerilyn Maloney ,  Chandan Bhat

IPC: H01L23/049 ,  H01L23/24 ,  H01L23/31 ,  H01L21/56

Abstract: A chip package and method for fabricating the same are provided which utilize a cover having one or more windows formed through one or more sidewalls to provide excellent resistance to warpage while allowing access to an internal volume of the chip package. In one example, the chip package includes a package substrate, an integrated circuit (IC) die, and a cover disposed over the IC die. The cover includes a lower surface facing the IC die, an upper surface facing away from the IC die, a lip extending from the lower surface, and a first sidewall extending from a first edge of the upper surface to the bottom of the lip. The lip is secured to the package substrate and encloses a volume between the lower surface and the package substrate. The IC die resides in the volume. A first elongated window is formed through the first sidewall and exposes the volume through the cover.

公开(公告)号：US10438863B1

公开(公告)日：2019-10-08

申请号：US16138671

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Ronilo Boja ,  Inderjit Singh

IPC: H01L23/31 ,  H01L21/52 ,  H01L23/488

Abstract: A chip package assembly, a package substrate and methods for fabricating the same are disclosed herein. In one example, a chip package assembly includes a package substrate, an IC die and a stiffener. The package substrate includes a first dam projecting from a top surface of the package substrate. The IC die and the stiffener are mounted to the top surface of the package substrate. The stiffener includes a bottom surface that is disposed adjacent to the first dam. At least one surface mounted component is mounted to a region of the package substrate defined between the stiffener and the IC die. An adhesive coupling the stiffener to the package substrate is in contact with the first dam.

公开(公告)号：US10764996B1

公开(公告)日：2020-09-01

申请号：US16012594

申请日：2018-06-19

Applicant: Xilinx, Inc.

Inventor： Ronilo Boja ,  Inderjit Singh

IPC: H05K1/02 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/10 ,  H01L23/40

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a composite stiffener selected to provide excellent resistance to warpage without detrimentally imposing excessive stress on a package substrate of the package assembly. In one example, the chip package assembly includes an integrated circuit die stacked on a top surface of a package substrate, and a composite stiffener coupled to a first edge of the package substrate. The composite stiffener includes a first stiffener member and a second stiffener member. The first stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member is disposed over the first stiffener member. The second stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member has a Young's modulus that is less than a Young's modulus of the first stiffener member.